Freescale-semiconductor MPC5200B Instrukcja Użytkownika

MPC5200B Users GuideDocument Number: MPC5200BUGRev. 105/2005

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-911.3.3.5 ATA Drive Error Register—MBAR + 0x3A64

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-55Pin ETH_6 Ball N02GPIO hi - z GPIOSimple General Purpose OutputUSB2 hi

MPC5200B Users Guide, Rev. 12-56 Freescale SemiconductorPinout TablesNotes: 1. The external bus clock (pci_clk) will be 1/2 the frequency of the inte

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-57Table 2-21. Ethernet Input / Control Functions by PinPIN / BALL NUMBER FunctionRe

MPC5200B Users Guide, Rev. 12-58 Freescale SemiconductorPinout TablesPin ETH_10 Ball J03GPIO hi - z GPIOSimple General Purpose OutputUSB2 hi

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-59Pin ETH_12 Ball M02GPIO hi - zUSB2 hi - zETH7 Wire hi - z ETH_RXD0Eth

MPC5200B Users Guide, Rev. 12-60 Freescale SemiconductorPinout TablesPin ETH_14 Ball N04GPIO hi - z INTERRUPTUSB2 hi - z USB_2_RXPUSB Receiv

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-61Pin ETH_16 Ball L02GPIO hi - z INTERRUPTUSB2 hi - z USB_2_OVRCNTUSB O

MPC5200B Users Guide, Rev. 12-62 Freescale SemiconductorPinout TablesFigure 2-10. Timer Port Map—8 PinsTable 2-22. Timer Pin FunctionsPin Name Dir. GP

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-63Table 2-23. Timer Functions by PinPIN / BALL NUMBER FunctionResetValueDescription

MPC5200B Users Guide, Rev. 12-64 Freescale SemiconductorPinout TablesPin TIMER_3 Ball D02TIMER hi - z TIMER_3GPIO hi - z GPIOSimple General

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-10 Freescale Semiconductor12.4.3.2 USB HC Period Current Endpoint Descript

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-65Figure 2-11. PSC6 Port Map—4 PinsPin TIMER_6 Ball E02TIMER hi - z TIMER

MPC5200B Users Guide, Rev. 12-66 Freescale SemiconductorPinout TablesTable 2-24. PSC6 Pin FunctionsPin name Dir. GPIO UART6/ IrDA CODEC6 / IrDAPSC6_0

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-67Figure 2-12. I2C Port Map—4 Pins (two pins each, for two I2Cs)Table 2-26. I2C Fun

MPC5200B Users Guide, Rev. 12-68 Freescale SemiconductorPinout TablesTable 2-27. SDRAM Bus Pin FunctionsPIN BALL NUMBER FunctionResetValueDescriptionP

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-69Pin MEM_MA_11Ball E20logic 0 SDRAM Bus Memory Address 11Pin MEM_MA_10Ball B17l

MPC5200B Users Guide, Rev. 12-70 Freescale SemiconductorPinout TablesPin MEM_MDQ_24Ball M18hi - z SDRAM Bus Data 24Pin MEM_MDQ_23Ball K18hi - z

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-71Pin MEM_MDQ_5Ball R19hi - z SDRAM Bus Data 5Pin MEM_MDQ_4Ball R20hi - z SDRAM

MPC5200B Users Guide, Rev. 12-72 Freescale SemiconductorPinout TablesTable 2-29. CLOCK / RESET Pin FunctionsCLOCK / RESET FunctionsReset ValueDescript

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-73Pin LP_OEBall D08logic 1 LocalPlus Bus Output EnablePin IRQ0Ball P03 External

Signal DescriptionsNotesMPC5200B Users Guide, Rev. 12-74 Freescale Semiconductor

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-1113.12.22 SDMA Initiator Priority 24 Register—MBA

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 3-1Chapter 3 Memory Map3.1 OverviewThe following sections are contained in this document:•

MPC5200B Users Guide, Rev. 13-2 Freescale SemiconductorInternal Register Memory Map3.2 Internal Register Memory MapTable 3-1. Internal Register Memory

MPC5200B Memory MapMPC5200B Users Guide, Rev. 1Freescale Semiconductor 3-33.3 MPC5200B Memory MapThe MPC5200B memory map has the following main region

MPC5200B Users Guide, Rev. 13-4 Freescale SemiconductorMPC5200B Memory Map3.3.2.2 LocalPlus BusThe LocalPlus Bus is designed to connect to ROM, FLASH,

MPC5200B Memory MapMPC5200B Users Guide, Rev. 1Freescale Semiconductor 3-53.3.3 Memory Map Space Register DescriptionThese registers exist in the Memo

MPC5200B Users Guide, Rev. 13-6 Freescale SemiconductorMPC5200B Memory MapAll of these Base Address Registers work the same3.3.3.3 SDRAM Chip Select C

MPC5200B Memory MapMPC5200B Users Guide, Rev. 1Freescale Semiconductor 3-7msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R Base XLB Address ReservedWRESET 0

MPC5200B Users Guide, Rev. 13-8 Freescale SemiconductorMPC5200B Memory Map3.3.3.4 IPBI Control Register and Wait State Enable —MBAR+0x0054The IPBI Con

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 4-1Chapter 4 Resets and Reset Configuration4.1 OverviewThe following sections are containe

MPC5200B Users Guide, Rev. 14-2 Freescale SemiconductorReset Sequence4.2.3 Soft Reset—SRESETExternal SRESET is an open drain signal. SRESET requires a

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-12 Freescale Semiconductor14.5.17 FEC Descriptor Individual Address 2 Regi

Other ResetsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 4-3Figure 4-2. PORRESET AssertionWhen external HRESET is asserted, internal reset logi

MPC5200B Users Guide, Rev. 14-4 Freescale SemiconductorReset Configuration4.6 Reset ConfigurationThe MPC5200B is initialized by sampling values found

Reset ConfigurationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 4-5L03 RST_CFG13 ETH5 PORCFG[18] boot_rom_size For non-muxed boot ROMs: 2,3bit

Resets and Reset ConfigurationNotesMPC5200B Users Guide, Rev. 14-6 Freescale Semiconductor

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-1Chapter 5 Clocks and Power Management5.1 OverviewThe following sections are contained i

MPC5200B Users Guide, Rev. 15-2 Freescale SemiconductorMPC5200B Clock Domains— When generated externally, the frequency can be differentNOTEOnly one p

MPC5200B Clock DomainsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-35.3.1 MPC5200B Top Level Clock RelationsFigure 5-2 shows the CDM clock di

MPC5200B Users Guide, Rev. 15-4 Freescale SemiconductorMPC5200B Clock DomainsTable 5-2 shows the System PLL configuration and the corresponding fsyste

MPC5200B Clock DomainsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-5Table 5-4 shows the typical clock ratios with a 33.0 MHz clock input on t

MPC5200B Users Guide, Rev. 15-6 Freescale SemiconductorMPC5200B Clock DomainsTable 5-6 gives the e300 Core APLL and operating frequency options compar

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-1315.2.14 Codec Clock Register (0x20)—CCR ...

MPC5200B Clock DomainsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-7NOTEThe XLB CLOCK frequency and the ppc_pll_cfg[0:4] must be chosen such

MPC5200B Users Guide, Rev. 15-8 Freescale SemiconductorMPC5200B Clock DomainsFigure 5-3 shows the clock relationships for the SDRAM Controller.Figure

Power ManagementMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-95.4 Power ManagementPower Management modes are listed below. Details are given

MPC5200B Users Guide, Rev. 15-10 Freescale SemiconductorPower Management5.4.3.1 Dynamic Power ModeThis is the default power state mode. The core is fu

CDM RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-11mode. The e300 Core must enable the deep sleep process in the CDM module, then pu

MPC5200B Users Guide, Rev. 15-12 Freescale SemiconductorCDM Registers5.5.1 CDM JTAG ID Number Register—MBAR + 0x0200The CDM JTAG ID Number Register is

CDM RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-1315 sys_pll_bypass bit=0:Normal mode. The SYS OSC clock input is multiplied up by

MPC5200B Users Guide, Rev. 15-14 Freescale SemiconductorCDM Registers5.5.3 CDM Bread Crumb Register—MBAR + 0x0208The CDM Bread Crumb Register is a 32-

CDM RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-15NOTEThe clock ratio should only be changed if no module, which is clocked by the

MPC5200B Users Guide, Rev. 15-16 Freescale SemiconductorCDM Registers5.5.6 CDM Clock Enable Register—MBAR + 0x0214The CDM Clock Enable Register, or po

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-14 Freescale Semiconductor15.3.3.4 Configuration Sequence for AC97 Mode ..

CDM RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-175.5.7 CDM System Oscillator Configuration Register—MBAR + 0x0218This register con

MPC5200B Users Guide, Rev. 15-18 Freescale SemiconductorCDM Registers5.5.8 CDM Clock Control Sequencer Configuration Register—MBAR + 0x021CThis regist

CDM RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-1916–30 — Reserved for future use. Write 0.31 ccs_qreq_test CCS Test bit—Used in CC

MPC5200B Users Guide, Rev. 15-20 Freescale SemiconductorCDM Registers5.5.9 CDM Soft Reset Register—MBAR + 0x0220This register contains 2 reset control

CDM RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-215.5.11 PSC1 Mclock Config Register—MBAR + 0x0228This register controls the genera

MPC5200B Users Guide, Rev. 15-22 Freescale SemiconductorCDM Registers5.5.12 PSC2 Mclock Config Register—MBAR + 0x022CThis register controls the genera

CDM RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 5-235.5.14 PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234This register controls the

MPC5200B Users Guide, Rev. 15-24 Freescale SemiconductorCDM Registers

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 6-1Chapter 6 e300 Processor Core6.1 OverviewThe following sections are contained in this d

MPC5200B Users Guide, Rev. 16-2 Freescale Semiconductore300 Core Reference Manual6.3 e300 Core Reference Manual A complete specification for the e300

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-15Chapter 17 Serial Peripheral Interface (SPI)17.1

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-1Chapter 7 System Integration Unit (SIU)7.1 OverviewThe following sections are contained

MPC5200B Users Guide, Rev. 17-2 Freescale SemiconductorInterrupt ControllerTable 7-1 does not include machine-check bus errors or transaction handshak

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-3Figure 7-1. Interrupt Sources and e300 core Interrupt PinsIRQ[0:3] Interrup

MPC5200B Users Guide, Rev. 17-4 Freescale SemiconductorInterrupt Controller7.2.2 Interface DescriptionFigure 7-2. Interrupt Controller Routing Scheme7

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-5correct behavior, the e300 core always completes the core_int before treati

MPC5200B Users Guide, Rev. 17-6 Freescale SemiconductorInterrupt ControllerBits Name Description— Per_mask Bits 0:23—To mask/accept individual periphe

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-77.2.4.2 ICTL Peripheral Priority and HI/LO Select 1 Register —MBAR + 0x0504

MPC5200B Users Guide, Rev. 17-8 Freescale SemiconductorInterrupt Controller7.2.4.3 ICTL Peripheral Priority and HI/LO Select 2 Register —MBAR + 0x0508

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-97.2.4.5 ICTL External Enable and External Types Register —MBAR + 0x0510 8:1

MPC5200B Users Guide, Rev. 17-10 Freescale SemiconductorInterrupt Controller7.2.4.6 ICTL Critical Priority and Main Interrupt Mask Register—MBAR + 0x0

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-16 Freescale Semiconductor19.5.4 MSCAN Control Register 1 (CANCTL1)—MBAR +

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-11— Main_Mask[x] To mask/accept individual main interrupt sources (as oppose

MPC5200B Users Guide, Rev. 17-12 Freescale SemiconductorInterrupt Controller7.2.4.7 ICTL Main Interrupt Priority and INT/SMI Select 1 Register —MBAR +

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-137.2.4.8 ICTL Main Interrupt Priority and INT/SMI Select 2 Register—MBAR +

MPC5200B Users Guide, Rev. 17-14 Freescale SemiconductorInterrupt Controller7.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register—MBAR +

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-157.2.4.10 ICTL Critical Interrupt Status All Register—MBAR + 0x0528 21:23 C

MPC5200B Users Guide, Rev. 17-16 Freescale SemiconductorInterrupt Controller7.2.4.11 ICTL Main Interrupt Status All Register—MBAR + 0x052C Bits Name D

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-177.2.4.12 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0530 23 MS

MPC5200B Users Guide, Rev. 17-18 Freescale SemiconductorInterrupt Controller7.2.4.13 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0538 16 PS

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-197.2.4.14 ICTL Main Interrupt Emulation All Register—MBAR + 0x0540 Table 7-

MPC5200B Users Guide, Rev. 17-20 Freescale SemiconductorInterrupt Controller7.2.4.15 ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544 Ta

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-17Chapter 20 Byte Data Link Controller (BDLC)20.1

Interrupt ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-217.2.4.16 ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548 27 PEa17

MPC5200B Users Guide, Rev. 17-22 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3 General Purpose I/O (GPIO)There are a total of 56 possible GPIO

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-23PSC1_0 UART1/AC971/CODEC1 No NoPSC1_1 UART1/AC971/CODEC1 No NoPSC1_2

MPC5200B Users Guide, Rev. 17-24 Freescale SemiconductorGeneral Purpose I/O (GPIO)GPIO_ETHI_2 Ethernet No NoGPIO_ETHI_3 Ethernet No NoGPIO_SINT_4(ETH)

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-257.3.1 GPIO Pin MultiplexingFigure 7-3 shows the GPIO/Generic MUX cel

MPC5200B Users Guide, Rev. 17-26 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.1.1 PSC1 (UART1/AC97/CODEC1)The PSC1 port has 5 pins with hardwa

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-27Full Ethernet consumes all 18 pins, unless the optional MDIO and MDC

MPC5200B Users Guide, Rev. 17-28 Freescale SemiconductorGeneral Purpose I/O (GPIO)• Timer pins 6 and 7 are dedicated as Timer GPIO and have no alterna

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-297.3.2.1.1 GPS Port Configuration Register—MBAR + 0x0B00 Table 7-21.

MPC5200B Users Guide, Rev. 17-30 Freescale SemiconductorGeneral Purpose I/O (GPIO)9:11 IRDA Infrared Data Association000 = All IrDA pins are GPIOs001

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-18 Freescale Semiconductor20.8.8.1 Transmitting Or Receiving A Block Mode

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-317.3.2.1.2 GPS Simple GPIO Enables Register—MBAR + 0x0B04 20:23 PSC3

MPC5200B Users Guide, Rev. 17-32 Freescale SemiconductorGeneral Purpose I/O (GPIO)R Reserved IRDA ETHR Reserved USBW16 17 18 19 20 21 22 23 24 25 26 2

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-337.3.2.1.3 GPS Simple GPIO Open Drain Type Register —MBAR + 0x0B08 24

MPC5200B Users Guide, Rev. 17-34 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.1.4 GPS Simple GPIO Data Direction Register—MBAR + 0x0B0C 12:1

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-35Bit Name Description0:1 — Reserved2:3 IRDA Individual bits to contro

MPC5200B Users Guide, Rev. 17-36 Freescale SemiconductorGeneral Purpose I/O (GPIO)24:27 PSC2 Individual bits to control directionality of the pin as G

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-377.3.2.1.5 GPS Simple GPIO Data Output Values Register —MBAR + 0x0B10

MPC5200B Users Guide, Rev. 17-38 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.1.6 GPS Simple GPIO Data Input Values Register —MBAR + 0x0B14

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-397.3.2.1.7 GPS GPIO Output-Only Enables Register —MBAR + 0x0B18 12:15

MPC5200B Users Guide, Rev. 17-40 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.1.8 GPS GPIO Output-Only Data Value Out Register —MBAR + 0x0B1

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-1Chapter 1 Introduction1.1 Overview ...

List of FiguresFigure PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor LOF-11-1 Simplified Block Diagram—MPC5200 ...

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-417.3.2.1.9 GPS GPIO Simple Interrupt Enable Register—MBAR + 0x0B20 Bi

MPC5200B Users Guide, Rev. 17-42 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register —

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-437.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register —MBAR +

MPC5200B Users Guide, Rev. 17-44 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-457.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register —MBAR

MPC5200B Users Guide, Rev. 17-46 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.1.16 GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C B

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-477.3.2.2 WakeUp GPIO Registers—MBAR+0x0C00The WakeUp GPIO Register Se

MPC5200B Users Guide, Rev. 17-48 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register —MBAR + 0x0C

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-497.3.2.2.4 GPW WakeUp GPIO Data Value Out Register —MBAR + 0x0C0C Bit

MPC5200B Users Guide, Rev. 17-50 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.2.5 GPW WakeUp GPIO Interrupt Enable Register—MBAR + 0x0C10 7.

List of FiguresFigure PageNumber NumberMPC5200B Users Guide, Rev. 1LOF-2 Freescale Semiconductor12-2 Communication Channels ...

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-517.3.2.2.7 GPW WakeUp GPIO Interrupt Types Register—MBAR + 0x0C18 Bit

MPC5200B Users Guide, Rev. 17-52 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.2.8 GPW WakeUp GPIO Master Enables Register —MBAR + 0x0C1C Bit

General Purpose I/O (GPIO)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-537.3.2.2.9 GPW WakeUp GPIO Data Input Values Register —MBAR + 0x0C20

MPC5200B Users Guide, Rev. 17-54 Freescale SemiconductorGeneral Purpose I/O (GPIO)7.3.2.2.10 GPW WakeUp GPIO Status Register—MBAR + 0x0C24 Table 7-46.

General Purpose Timers (GPT)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-557.4 General Purpose Timers (GPT)Eight (8) General-Purpose Timer (G

MPC5200B Users Guide, Rev. 17-56 Freescale SemiconductorGeneral Purpose Timers (GPT)7.4.4 GPT Registers—MBAR + 0x0600Each GPT uses 4 32-bit registers.

General Purpose Timers (GPT)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-57Bit Name Description0:7 OCPW Output Compare Pulse Width—Applies to

MPC5200B Users Guide, Rev. 17-58 Freescale SemiconductorGeneral Purpose Timers (GPT)21 Stop_Cont Stop Continuous—Applies to multiple modes, as follows

General Purpose Timers (GPT)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-597.4.4.2 GPT 0 Counter Input Register—MBAR + 0x0604GPT 1 Counter In

MPC5200B Users Guide, Rev. 17-60 Freescale SemiconductorGeneral Purpose Timers (GPT)7.4.4.3 GPT 0 PWM Configuration Register—MBAR + 0x0608GPT 1 PWM Co

List of FiguresFigure PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor LOF-319-11 Initialization Request/Acknowledge Cycle ...

General Purpose Timers (GPT)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-617.4.4.4 GPT 0 Status Register—MBAR + 0x060CGPT 1 Status Register—M

MPC5200B Users Guide, Rev. 17-62 Freescale SemiconductorSlice Timers7.5 Slice TimersTwo Slice Timers are included to provide shorter term periodic int

Slice TimersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-637.5.1.1 SLT 0 Terminal Count Register—MBAR + 0x0700SLT 1 Terminal Count Register—M

MPC5200B Users Guide, Rev. 17-64 Freescale SemiconductorSlice Timers7.5.1.3 SLT 0 Count Value Register—MBAR + 0x0708SLT 1 Count Value Register—MBAR +

Real-Time ClockMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-657.5.1.4 SLT 0 Timer Status Register—MBAR + 0x070CSLT 1 Timer Status Register—MB

MPC5200B Users Guide, Rev. 17-66 Freescale SemiconductorReal-Time ClockPeriodic interrupts are separately enabled by control bits, and a global enable

Real-Time ClockMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-677.6.3.1 RTC Time Set Register—MBAR + 0x0800 • RTC New Year and Stopwatch Regist

MPC5200B Users Guide, Rev. 17-68 Freescale SemiconductorReal-Time Clock7.6.3.2 RTC Date Set Register—MBAR + 0x0804 18:23 Minute_set Minute written in

Real-Time ClockMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-697.6.3.3 RTC New Year and Stopwatch Register—MBAR + 0x0808 7.6.3.4 RTC Alarm and

MPC5200B Users Guide, Rev. 17-70 Freescale SemiconductorReal-Time Clock7.6.3.5 RTC Current Time Register—MBAR + 0x0810This is a read-only register. 8:

List of FiguresMPC5200B Users Guide, Rev. 1LOF-4 Freescale SemiconductorNotes

Real-Time ClockMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-717.6.3.6 RTC Current Date Register—MBAR + 0x0814This is a read-only register. 7.

MPC5200B Users Guide, Rev. 17-72 Freescale SemiconductorReal-Time Clock7.6.3.8 RTC Periodic Interrupt and Bus Error Register—MBAR + 0x081CThis is a re

Real-Time ClockMPC5200B Users Guide, Rev. 1Freescale Semiconductor 7-737.6.3.9 RTC Test Register/Divides Register—MBAR + 0x0820This register is used d

MPC5200B Users Guide, Rev. 17-74 Freescale SemiconductorReal-Time Clock

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-1Chapter 8 SDRAM Memory Controller8.1 OverviewThe following sections are contained in th

MPC5200B Users Guide, Rev. 18-2 Freescale SemiconductorFeaturesstripped along the way). Nor is the transportation of data an execution context. Withou

FeaturesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-3— 2 bits of bank address (BA[1:0])NOTEIn this document the Auto Precharge control signa

MPC5200B Users Guide, Rev. 18-4 Freescale SemiconductorFeaturesTable 8-1. 32-Bit External Data Width Legal Memory ConfigurationsRow Bits Column Bits B

FeaturesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-512131211221 4 x 512Mb16M x 4bank x 8bit256MB2 x 1Gb16M x 4bank x 16bit1 x 2Gb16M x 4ban

MPC5200B Users Guide, Rev. 18-6 Freescale SemiconductorFeatures12 8 2 1 2 x 64Mb1M x 4bank x 16bit144MB+121311102 1 2 x 512Mb8M x 4bank x 16bit12 8 2

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor LOT-12-1 Signals by Ball/Pin ...

FeaturesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-713 8 2 1 2 x 128Mb2M x 4bank x 16bit160MB+13 10 2 1 2 x 512Mb8M x 4bank x 16bit12 9 2 1

MPC5200B Users Guide, Rev. 18-8 Freescale SemiconductorFeatures12 10 2 1 2 x256Mb4M x 4bank x 16bit192MB+12 11 2 1 2 x 512Mb8M x 4bank x 16bit13 9 2 1

FeaturesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-913 9 2 1 2 x 512Mb8M x 4bank x 32bit384MB+13 11 2 1 2 x 1Gb16M x 4bank x 32bit12 11 2 1

MPC5200B Users Guide, Rev. 18-10 Freescale SemiconductorFeatures13 10 2 1 2 x 256Mb8M x 4bank x 8bit64MB1 x 512Mb8M x 4bank x 16bit2 4 x 256Mb8M x 4ba

FeaturesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-1112 9 2 1 2 x 64Mb2M x 4bank x 8bit144MB+13 11 2 1 1 x 1Gb16M x 4bank x 16bit12 9 2 1 1

MPC5200B Users Guide, Rev. 18-12 Freescale SemiconductorFeatures12 10 2 1 2 x 128Mb4M x 4bank x 8bit160MB+13 11 2 1 2 x 256Mb16M x 4bank x 8bit12 10 2

FeaturesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-1313 11 2 1 2 x 512Mb16M x 4bank x 8bit256MB+13 11 2 1 1 x 1Gb16M x 4bank x 16bitTable 8

MPC5200B Users Guide, Rev. 18-14 Freescale SemiconductorFeaturesFigure 8-1 shows an example memory configuration of 1 space (CS) of 4 devices of 128Mb

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-158.4 Functional Description8.4.1 External Signals (SDRAM Side)Table 8-3.

MPC5200B Users Guide, Rev. 18-16 Freescale SemiconductorFunctional Description8.4.2 Block DiagramFigure 8-2 shows the SDRAM MC block diagram. It is im

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1LOT-2 Freescale Semiconductor5-19 CDM PSC2 Mclock Config ...

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-17modulo 8 boundary within the modulo 32 range; the address “wraps” from t

MPC5200B Users Guide, Rev. 18-18 Freescale SemiconductorFunctional DescriptionSome of the configuration parameters required by the memory are also nee

OperationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-19With both SDR and DDR memory, a Read command can be issued overlapping the masked bea

MPC5200B Users Guide, Rev. 18-20 Freescale SemiconductorProgramming the SDRAM ControllerIf all the memory and controller register values have been pre

Memory Controller Registers (MBAR+0x0100:0x010C)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-21 Table 8-5. Memory Controller Mode Registermsb

MPC5200B Users Guide, Rev. 18-22 Freescale SemiconductorMemory Controller Registers (MBAR+0x0100:0x010C)8.7.2 Control Register—MBAR + 0x0104The 32-bit

Memory Controller Registers (MBAR+0x0100:0x010C)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-23The Table 8-7 indicates how the internal addre

MPC5200B Users Guide, Rev. 18-24 Freescale SemiconductorMemory Controller Registers (MBAR+0x0100:0x010C)Table 8-8. 32-Bit SDRAM Address MultiplexingDe

Memory Controller Registers (MBAR+0x0100:0x010C)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-258.7.3 Configuration Register 1—MBAR + 0x0108Th

MPC5200B Users Guide, Rev. 18-26 Freescale SemiconductorMemory Controller Registers (MBAR+0x0100:0x010C)MEM_CLK2—double frequency of MEM_CLK—DDR uses

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor LOT-37-51 SLT 0 Terminal Count Register ...

Memory Controller Registers (MBAR+0x0100:0x010C)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-278.7.4 Configuration Register 2—MBAR + 0x010CTh

MPC5200B Users Guide, Rev. 18-28 Freescale SemiconductorMemory Controller Registers (MBAR+0x0100:0x010C)Bit Name Description0:3 brd2rp Burst Read to R

Memory Controller Registers (MBAR+0x0100:0x010C)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-29The Figure 8-3. Programmable Command Timings s

MPC5200B Users Guide, Rev. 18-30 Freescale SemiconductorAddress Bus Mapping8.8 Address Bus MappingFigure 8-4. Address Bus Mapping (32-Bit External Dat

Address Bus MappingMPC5200B Users Guide, Rev. 1Freescale Semiconductor 8-31Figure 8-5. Address Bus Mapping (16-Bit External Data Width)8.8.1 Example—P

MPC5200B Users Guide, Rev. 18-32 Freescale SemiconductorAddress Bus MappingBy default, the Memory Controller only provides 12 row address bits and 12

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-1Chapter 9 LocalPlus Bus (External Bus Interface)9.1 OverviewThe LocalPlus Bus is the ex

MPC5200B Users Guide, Rev. 19-2 Freescale SemiconductorInterface– (Address 8, 16, 24 or 25 bits, Data 8,16 or 32 bits, 2 Bank Selects)• 8 Chip Select

InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-39.3.2 Block DiagramThe block diagram of the LocalPlus Controller (LPC) is shown in Fig

MPC5200B Users Guide, Rev. 19-4 Freescale SemiconductorModes of OperationFigure 9-2. Muxed Mode Address Latching9.4 Modes of OperationThere are 2 prim

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1LOT-4 Freescale Semiconductor10-9 Special Cycle Message Encodings ...

Modes of OperationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-5NOTEThe 24-bit data width is not supported. The total pin number requires als

MPC5200B Users Guide, Rev. 19-6 Freescale SemiconductorModes of OperationFigure 9-4. Timing Diagram—Non-MUXed ModeFigure 9-5. Timing Diagram—Burst Mod

Modes of OperationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-7In this mode, the peripheral address and data lines are limited to a total of

MPC5200B Users Guide, Rev. 19-8 Freescale SemiconductorModes of OperationThe MUXed mode requires external logic to latch the address during the addres

ConfigurationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-9Figure 9-6 shows a MUXed transaction type timing diagram.Figure 9-6. Timing Diagra

MPC5200B Users Guide, Rev. 19-10 Freescale SemiconductorConfiguration• The boot address/exception table can be located at 0x0000 0100 or 0xfff0 0100.T

DMA (BestComm) Interface (SCLPC)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-11• BootSwapTable 9-1 describes possible boot settings.9.6 DMA (

MPC5200B Users Guide, Rev. 19-12 Freescale SemiconductorProgrammer’s Model• Section 9-10, Chip Select Status Register (0x031C)• Section 9-11, Chip Sel

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-139.7.1.1 Chip Select 0/Boot Configuration Register—MBAR + 0x0300 Table 9-7. C

MPC5200B Users Guide, Rev. 19-14 Freescale SemiconductorProgrammer’s Model20:21 AS Address Size field—defines size of peripheral Address bus (in bytes

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor LOT-512-8 USB HC Period Current Endpoint Descriptor Register

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-159.7.1.2 Chip Select 1 Configuration Register—MBAR + 0x0304Chip Select 2 Conf

MPC5200B Users Guide, Rev. 19-16 Freescale SemiconductorProgrammer’s Model16 MX MX bit specifies whether transaction operates as multiplexed or non-mu

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-179.7.1.3 Chip Select Control Register—MBAR + 0x0318 28 WS Write Swap bit—If h

MPC5200B Users Guide, Rev. 19-18 Freescale SemiconductorProgrammer’s Model9.7.1.4 Chip Select Status Register—MBAR + 0x031C 9.7.1.5 Chip Select Burst

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-1916 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsbR CW3 SLB3RsvdBRE3CW2 SLB

MPC5200B Users Guide, Rev. 19-20 Freescale SemiconductorProgrammer’s Model13 SLB4 Chip Select 4 Short/Long Burst, 0 for Short Burst only, 1 for Long B

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-219.7.1.6 Chip Select Deadcycle Control Register—MBAR + 0x032C 28 CW0 Chip Sel

MPC5200B Users Guide, Rev. 19-22 Freescale SemiconductorProgrammer’s ModelNOTEDeadcycle counter is only used, if no arbitration to an other module (AT

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-239.7.2 SCLPC Registers—MBAR + 0x3C00There are 6 32-bit BestComm Registers for

MPC5200B Users Guide, Rev. 19-24 Freescale SemiconductorProgrammer’s Model9.7.2.2 SCLPC Start Address Register—MBAR + 0x3C04 9.7.2.3 SCLPC Control Reg

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1LOT-6 Freescale Semiconductor14-1 Signal Properties ...

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-259.7.2.4 SCLPC Enable Register—MBAR + 0x3C0C 16:22 — Reserved23 DAI Disable A

LocalPlus Bus (External Bus Interface)NotesMPC5200B Users Guide, Rev. 19-26 Freescale Semiconductor9.7.2.5 SCLPC Bytes Done Status Register—MBAR + 0x3

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-277 NT Normal Termination. This bit is set to 1 whenever a complete Packet has

MPC5200B Users Guide, Rev. 19-28 Freescale SemiconductorProgrammer’s Model9.7.3 SCLPC FIFO Registers—MBAR + 0x3C40LPC uses a single FIFO that changes

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-299.7.3.2 LPC Rx/Tx FIFO Status Register—MBAR + 0x3C44 Bits Name Description0:

MPC5200B Users Guide, Rev. 19-30 Freescale SemiconductorProgrammer’s Model9.7.3.3 LPC Rx/Tx FIFO Control Register—MBAR + 0x3C48 9.7.3.4 LPC Rx/Tx FIFO

Programmer’s ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 9-319.7.3.5 LPC Rx/Tx FIFO Read Pointer Register—MBAR + 0x3C50 9.7.3.6 LPC Rx/Tx

LocalPlus Bus (External Bus Interface)NotesMPC5200B Users Guide, Rev. 19-32 Freescale Semiconductor

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-1Chapter 10 PCI Controller10.1 OverviewThe Peripheral Component Interface (PCI) Bus is

MPC5200B Users Guide, Rev. 110-2 Freescale SemiconductorPCI External Signals10.1.2 Block DiagramFigure 10-1. PCI Block Diagram10.2 PCI External Signal

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-2 Freescale Semiconductor4.2.2 Hard Reset—HRESET ...

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor LOT-715-9 Stop-Bit Lengths ...

PCI External SignalsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-3For detailed description of the PCI bus signals, see the PCI Local Bus Spe

MPC5200B Users Guide, Rev. 110-4 Freescale SemiconductorRegisters10.3 RegistersMPC5200B has several sets of registers that control and report status f

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-50x74 PCIIW1BTAR Initiator Window 1 Base/Translation Address Register0x78 PCIIW2BTAR I

MPC5200B Users Guide, Rev. 110-6 Freescale SemiconductorRegisters10.3.1 PCI Controller Type 0 Configuration SpaceMPC5200B supplies a type 0 PCI Config

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-7PCI Dword Reserved space (0x10 - 0x3F) can be accessed only from an external PCI Conf

MPC5200B Users Guide, Rev. 110-8 Freescale SemiconductorRegisters10.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) —MBAR + 0x0D04Bits 31-27 and 24 ar

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-99 Reserved(R)Fixed to 0. Prior to the 2.2 PCI Spec, this was the UDF (User Defined Fe

MPC5200B Users Guide, Rev. 110-10 Freescale SemiconductorRegisters10.3.1.3 Revision ID/ Class Code Registers PCICCRIR(R) —MBAR + 0x0D0810.3.1.4 Config

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-1110.3.1.5 Base Address Register 0 PCIBAR0(RW) —MBAR + 0x0D10Bits Name Description0:7

MPC5200B Users Guide, Rev. 110-12 Freescale SemiconductorRegisters10.3.1.6 Base Address Register 1 PCIBAR1(RW) —MBAR + 0x0D1410.3.1.7 CardBus CIS Poin

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1LOT-8 Freescale Semiconductor15-63 Tx FIFO Control (0x88) ...

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-1310.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)—MBAR + 0x0D34Not implemented. Fix

MPC5200B Users Guide, Rev. 110-14 Freescale SemiconductorRegisters16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsbRRsvd BME PEE SEE Reserved PRWRES

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-1520:30 Reserved Unused bits. Software should write zero to this register.31 PCIReset(

MPC5200B Users Guide, Rev. 110-16 Freescale SemiconductorRegisters10.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) —MBAR + 0x0D6410.3

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-1710.3.2.4 Target Control Register PCITCR(RW) —MBAR + 0x0D6CBits Name Description0:1 B

MPC5200B Users Guide, Rev. 110-18 Freescale SemiconductorRegisters10.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)—MBAR +

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-1910.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) —MBAR +

MPC5200B Users Guide, Rev. 110-20 Freescale SemiconductorRegisters10.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) —MBAR +

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-2110.3.2.9 Initiator Control Register PCIICR(RW) —MBAR + 0x0D848:11 Reserved Reserved

MPC5200B Users Guide, Rev. 110-22 Freescale SemiconductorRegisters10.3.2.10 Initiator Status Register PCIISR(RWC) —MBAR + 0x0D8810.3.2.11 PCI Arbiter

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor LOT-918-5 I2C Control Register ...

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-2310.3.2.12 Configuration Address Register PCICAR (RW) —MBAR + 0x0DF810.3.3 Communicat

MPC5200B Users Guide, Rev. 110-24 Freescale SemiconductorRegisters10.3.3.1.1 Tx Packet Size PCITPSR(RW) —MBAR + 0x3800 10.3.3.1.2 Tx Start Address PCI

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-2516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsbRReserved Max_Beats Reserved W Re

MPC5200B Users Guide, Rev. 110-26 Freescale SemiconductorRegisters10.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380Cmsb 012345678 9 101112131415RRCRFRsvd

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-2710.3.3.1.5 Tx Next Address PCITNAR(R) —MBAR + 0x3810 12 Retry abortEnable(RE)User wr

MPC5200B Users Guide, Rev. 110-28 Freescale SemiconductorRegisters10.3.3.1.6 Tx Last Word PCITLWR(R) —MBAR + 0x3814 10.3.3.1.7 Tx Bytes Done Counts PC

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-2910.3.3.1.9 Tx Status PCITSR(RWC) —MBAR + 0x381C 16 17 18 19 20 21 22 23 24 25 26 27

MPC5200B Users Guide, Rev. 110-30 Freescale SemiconductorRegisters10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) —MBAR + 0x3840 10 Bus Errortype 1(BE1)

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-3110.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) —MBAR + 0x3844 Bits Name Descript

MPC5200B Users Guide, Rev. 110-32 Freescale SemiconductorRegisters10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) —MBAR + 0x3848 10.3.3.1.13 Tx FIFO

List of TablesTable PageNumber NumberMPC5200B Users Guide, Rev. 1LOT-10 Freescale Semiconductor20-16 BDLC Receiver VPW Symbol Timing for Binary Freque

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-3316 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsbRReserved Alarm AlarmWRESET 0 000

MPC5200B Users Guide, Rev. 110-34 Freescale SemiconductorRegisters10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) —MBAR + 0x3850 10.3.3.1.15 Tx

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-3510.3.3.2.1 Rx Packet Size PCIRPSR(RW) —MBAR + 0x3880 10.3.3.2.2 Rx Start Address PCI

MPC5200B Users Guide, Rev. 110-36 Freescale SemiconductorRegisters16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsbRReserved FB R Max_Beats Reserved

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-3710.3.3.2.4 Rx Enables PCIRER (RW) —MBAR + 0x388C msb 012345678 9 101112131415RRCRFFE

MPC5200B Users Guide, Rev. 110-38 Freescale SemiconductorRegisters10.3.3.2.5 Rx Next Address PCIRNAR(R) —MBAR + 0x3890 10.3.3.2.6 Rx Last Word PCIRLWR

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-3910.3.3.2.7 Rx Bytes Done Counts PCIRDCR(R) —MBAR + 0x3898 10.3.3.2.8 Rx Packets Done

MPC5200B Users Guide, Rev. 110-40 Freescale SemiconductorRegisters10.3.3.2.9 Rx Status PCIRSR (R/sw1) —MBAR + 0x389C Bits Name Description0:31 Packets

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-4110.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) —MBAR + 0x38C0 10.3.3.2.11 Rx FIFO Sta

MPC5200B Users Guide, Rev. 110-42 Freescale SemiconductorRegisters10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) —MBAR + 0x38C8R Reserved RXW UF OF

MPC5200B Users Guide, Rev. 1Freescale Semiconductor 1Revision HistoryRelease Date Author Summary of Changes0 26MAR2005 AS Initial Version0.1 26MAR2005

RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-4310.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) —MBAR + 0x38CC Bits Name Description0

MPC5200B Users Guide, Rev. 110-44 Freescale SemiconductorFunctional Description10.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) —MBAR + 0x38D0 1

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-45NOTEOnly the internal PCI arbiter of the MPC5200B can be used as PCI ar

MPC5200B Users Guide, Rev. 110-46 Freescale SemiconductorFunctional Descriptionor more data phases. Data is transferred between initiator and target i

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-47Figure 10-3. PCI Write Terminated by Target10.4.1.4 PCI Bus CommandsPCI

MPC5200B Users Guide, Rev. 110-48 Freescale SemiconductorFunctional DescriptionThough MPC5200B supports many PCI commands as an initiator, the Communi

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-49For linear incrementing mode, the memory address is encoded/decoded usi

MPC5200B Users Guide, Rev. 110-50 Freescale SemiconductorFunctional DescriptionFigure 10-4. Contents of the AD Bus During Address Phase of a Type 0 Co

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-5110.4.2 Initiator ArbitrationThere are three possible internal initiator

MPC5200B Users Guide, Rev. 110-52 Freescale SemiconductorFunctional DescriptionIn addition to the configurable address window mapping logic, the regis

MPC5200B Users Guide, Rev. 1Freescale Semiconductor

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-53101 001 -- -- -- -- -- OP7 -- -- 100 1101 -- -- OP7 --110 001 -- -- --

MPC5200B Users Guide, Rev. 110-54 Freescale SemiconductorFunctional Description10.4.4.2 Configuration MechanismIn order to support both Type 0 and Typ

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-55Figure 10-7. Type 0 Configuration TranslationFor Type 0 configuration c

MPC5200B Users Guide, Rev. 110-56 Freescale SemiconductorFunctional DescriptionNOTE: Device numbers 0b0_0000 to 0b0_1001 are reserved. Programming to

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-57During the data phase, AD[31:0] contain the Special Cycle message and a

MPC5200B Users Guide, Rev. 110-58 Freescale SemiconductorFunctional Description10.4.5.1 Reads from Local MemoryMPC5200B can provide continuous data to

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-5910.4.5.4 Target AbortA target abort will occur if the PCI address falls

MPC5200B Users Guide, Rev. 110-60 Freescale SemiconductorFunctional DescriptionThe Communication Sub-System Initiator Interface consists of Receive an

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-612. Set the PCI command, Max_Retries, and Max_Beats3. Set mode, Continuo

MPC5200B Users Guide, Rev. 110-62 Freescale SemiconductorPCI Arbiter10.4.6.8 AlarmsThe FIFO alarm registers allow software to control when the DMA fil

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 1-1Chapter 1 Introduction1.1 OverviewThe digital communication networking and consumer mar

Application InformationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-63The PCI Arbiter implements a Round-Robin fairness algorithm, which avo

MPC5200B Users Guide, Rev. 110-64 Freescale SemiconductorApplication Information10.6.2 Address MapsThe address mapping in MPC5200B system is setup by

Application InformationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-65Figure 10-8. Inbound Address Map10.6.2.1.2 Outbound Address Translatio

MPC5200B Users Guide, Rev. 110-66 Freescale SemiconductorApplication InformationFigure 10-9. Outbound Address Map10.6.2.1.3 Base Address Register Over

Application InformationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 10-6710.6.3 XL bus Arbitration PriorityWhen the XL Bus Arbiter Master Prior

MPC5200B Users Guide, Rev. 110-68 Freescale SemiconductorApplication Information

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-1Chapter 11 ATA Controller11.1 OverviewThe following sections are contained in this doc

MPC5200B Users Guide, Rev. 111-2 Freescale SemiconductorATA Register Interface4. As FIFO fills, BestComm is interrupted and moves data from FIFO to an

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-311.3.1.2 ATA Host Status Register—MBAR + 0x3A04 11.3.1.3 ATA PIO Timing

MPC5200B Users Guide, Rev. 111-4 Freescale SemiconductorATA Register Interface11.3.1.4 ATA PIO Timing 2 Register—MBAR + 0x3A0C 11.3.1.5 ATA Multiword

MPC5200B Users Guide, Rev. 11-2 Freescale SemiconductorArchitecture— IrDA mode from 2400 bps to 4 Mbps• Fast Ethernet Controller (FEC) — Supports 100M

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-511.3.1.6 ATA Multiword DMA Timing 2 Register—MBAR + 0x3A14 11.3.1.7 ATA

MPC5200B Users Guide, Rev. 111-6 Freescale SemiconductorATA Register Interface11.3.1.8 ATA Ultra DMA Timing 2 Register—MBAR + 0x3A1C 11.3.1.9 ATA Ultr

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-711.3.1.10 ATA Ultra DMA Timing 4 Register—MBAR + 0x3A24 Bits Name Descri

MPC5200B Users Guide, Rev. 111-8 Freescale SemiconductorATA Register Interface11.3.1.11 ATA Ultra DMA Timing 5 Register—MBAR + 0x3A28 11.3.1.12 ATA Sh

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-9ATA FIFO is controlled by 32-bit registers. These registers are located

MPC5200B Users Guide, Rev. 111-10 Freescale SemiconductorATA Register Interface11.3.2.3 ATA Rx/Tx FIFO Control Register—MBAR + 0x3A44 11.3.2.4 ATA Rx/

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-1111.3.2.5 ATA Rx/Tx FIFO Read Pointer Register—MBAR + 0x3A4C 11.3.2.6 AT

MPC5200B Users Guide, Rev. 111-12 Freescale SemiconductorATA Register Interface11.3.3 ATA Drive Registers—MBAR + 0x3A00The ATA drive registers are phy

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-1311.3.3.2 ATA Drive Alternate Status Register—MBAR + 0x3A5C 11.3.3.3 ATA

MPC5200B Users Guide, Rev. 111-14 Freescale SemiconductorATA Register Interface11.3.3.4 ATA Drive Features Register—MBAR + 0x3A64 11.3.3.5 ATA Drive E

ArchitectureMPC5200B Users Guide, Rev. 1Freescale Semiconductor 1-3A dynamically managed external pin multiplexing scheme minimizes overall pin count.

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-1511.3.3.6 ATA Drive Sector Count Register—MBAR + 0x3A68 11.3.3.7 ATA Dri

MPC5200B Users Guide, Rev. 111-16 Freescale SemiconductorATA Register Interface11.3.3.8 ATA Drive Cylinder Low Register—MBAR + 0x3A70 11.3.3.9 ATA Dri

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-1711.3.3.10 ATA Drive Device/Head Register—MBAR + 0x3A78 11.3.3.11 ATA Dr

MPC5200B Users Guide, Rev. 111-18 Freescale SemiconductorATA Register InterfaceBits Name Description0:7 Data Register contains the command code sent t

ATA Register InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-1911.3.3.12 ATA Drive Device Status Register—MBAR + 0x3A7C Table 11-30. A

MPC5200B Users Guide, Rev. 111-20 Freescale SemiconductorATA Host Controller Operation11.4 ATA Host Controller OperationWith the asynchronous ATA inte

ATA Host Controller OperationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-21udma_t2cyc is another special case. Unlike the name implies, thi

MPC5200B Users Guide, Rev. 111-22 Freescale SemiconductorATA Host Controller OperationIf ATA drive address space is accessed by CPU, the ATA IPBI modu

Signals and ConnectionsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-2311.5 Signals and ConnectionsNOTEThe ATA_ISOLATION output is an active

MPC5200B Users Guide, Rev. 111-24 Freescale SemiconductorATA Interface DescriptionFigure 11-2. Connections—Controller Cable, System Board, MPC5200B11.

MPC5200B Users Guide, Rev. 11-4 Freescale SemiconductorArchitectureThe MPC5200B supports a dual external bus architecture consisting of:1. an SDRAM Bu

ATA Interface DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-25NOTEMPC5200B provides the ATA_ISOLATION output signal. This signal i

MPC5200B Users Guide, Rev. 111-26 Freescale SemiconductorATA Bus BackgroundFigure 11-3. Pin Description—ATA Interface11.7 ATA Bus Background11.7.1 Ter

ATA Bus BackgroundMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-2711.7.2 ATA Modes11.7.3 ATA AddressingIn the ATA interface, there are two as

MPC5200B Users Guide, Rev. 111-28 Freescale SemiconductorATA Bus Background11.7.3.1 ATA Register AddressingThe address used to reference an ATA drive

ATA Bus BackgroundMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-29Notes1. LBA mode is only available in ATA-2 or later specifications.2. A bl

MPC5200B Users Guide, Rev. 111-30 Freescale SemiconductorATA Bus Background11.7.4 ATA TransactionsATA Transactions are divided into three types:• PIO

ATA Bus BackgroundMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-31Figure 11-5. Timing Diagram—PIO Read Command (Class 1)11.7.4.1.2 Class 2—PI

MPC5200B Users Guide, Rev. 111-32 Freescale SemiconductorATA Bus BackgroundFigure 11-6. Timing Diagram—PIO Write Command (Class 2)11.7.4.1.3 Class 3—N

ATA Bus BackgroundMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-333. Write command code 0xEF to command register to execute SET FEATURES comm

MPC5200B Users Guide, Rev. 111-34 Freescale SemiconductorATA Bus BackgroundFigure 11-8. Flow Diagram—DMA Command ProtocolHost:BSY = 0 &DRQ = 0NoHo

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-3Chapter 7 System Integration Unit (SIU)7.1 Overvi

ArchitectureMPC5200B Users Guide, Rev. 1Freescale Semiconductor 1-5Figure 1-2. MPC5200B-Based System1.2.1 Embedded e300 CoreThe MPC5200B embedded e300

ATA Bus BackgroundMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-3511.7.4.3 Multiword DMA TransactionsMultiword DMA transactions differ from P

MPC5200B Users Guide, Rev. 111-36 Freescale SemiconductorATA RESET/Power-UpNOTEUltra DMA mode 2 (UDMA2) requires that the ip bus clock speed is at lea

ATA I/O Cable SpecificationsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 11-37Figure 11-10. Timing Diagram—Reset Timing11.9 ATA I/O Cable Speci

ATA ControllerNotesMPC5200B Users Guide, Rev. 111-38 Freescale Semiconductor

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-1Chapter 12 Universal Serial Bus (USB)12.1 OverviewThe following sections are contained

MPC5200B Users Guide, Rev. 112-2 Freescale SemiconductorHost Controller Interface• Bulk Transfers—Non-periodic data transfers used to communicate larg

Host Controller InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-3The HCCA includes the “virtual” registers HccaFrameNumber and HccaPad

MPC5200B Users Guide, Rev. 112-4 Freescale SemiconductorHost Controller InterfaceFigure 12-4. Interrupt ED StructureFigure 12-5 shows a sample interru

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-5Figure 12-5. Sample Interrupt Endpoint Schedule12.4 Hos

MPC5200B Users Guide, Rev. 112-6 Freescale SemiconductorHost Control (HC) Operational Registers12.4.2 Control and Status Partition—MBAR + 0x1000This H

MPC5200B Users Guide, Rev. 11-6 Freescale SemiconductorArchitectureUp to 3 instructions can be issued and retired per clock. Most instructions execute

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-7Bits Name Description0:20 — Reserved21 RWE RemoteWakeUp

MPC5200B Users Guide, Rev. 112-8 Freescale SemiconductorHost Control (HC) Operational Registers12.4.2.3 USB HC Command Status Register—MBAR + 0x1008HC

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-912.4.2.4 USB HC Interrupt Status Register —MBAR + 0x100

MPC5200B Users Guide, Rev. 112-10 Freescale SemiconductorHost Control (HC) Operational Registers12.4.2.5 USB HC Interrupt Enable Register—MBAR + 0x101

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-1112.4.2.6 USB HC Interrupt Disable Register—MBAR + 0x10

MPC5200B Users Guide, Rev. 112-12 Freescale SemiconductorHost Control (HC) Operational Registers12.4.3 Memory Pointer Partition—MBAR + 0x1018This HC p

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-13• USB HC Bulk Current Endpint Descriptor Register (0x1

MPC5200B Users Guide, Rev. 112-14 Freescale SemiconductorHost Control (HC) Operational Registers12.4.3.3 USB HC Control Head Endpoint Descriptor Regis

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-15 12.4.3.6 USB HC Bulk Current Endpoint Descriptor Regi

MPC5200B Users Guide, Rev. 112-16 Freescale SemiconductorHost Control (HC) Operational Registers 12.4.4 Frame Counter Partition—MBAR + 0x1034This HC p

ArchitectureMPC5200B Users Guide, Rev. 1Freescale Semiconductor 1-7MSCAN supports both standard and extended identifier (ID) message formats specified

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-1712.4.4.2 USB HC Frame Remaining Register—MBAR + 0x1038

MPC5200B Users Guide, Rev. 112-18 Freescale SemiconductorHost Control (HC) Operational Registers12.4.4.4 USB HC Periodic Start Register—MBAR + 0x1040T

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-1912.4.5 Root Hub Partition—MBAR + 0x1048This HC partiti

MPC5200B Users Guide, Rev. 112-20 Freescale SemiconductorHost Control (HC) Operational Registers12.4.5.2 USB HC Rh Descriptor B Register—MBAR + 0x104C

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-21 12.4.5.3 USB HC Rh Status Register—MBAR + 0x1050This

MPC5200B Users Guide, Rev. 112-22 Freescale SemiconductorHost Control (HC) Operational Registers12.4.5.4 USB HC Rh Port1 Status Register—MBAR + 0x1054

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-23 Table 12-22. USB HC Rh Port1 Status Registermsb 01234

MPC5200B Users Guide, Rev. 112-24 Freescale SemiconductorHost Control (HC) Operational Registers15 CSC ConnectStatusChange—bit is set whenever a conne

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-2528 POCI PortOverCurrentIndicator (read)—bit is only va

MPC5200B Users Guide, Rev. 112-26 Freescale SemiconductorHost Control (HC) Operational Registers12.4.5.5 USB HC Rh Port2 Status Register—MBAR + 0x1058

MPC5200B Users Guide, Rev. 11-8 Freescale SemiconductorArchitecture1.2.5.5 Functional Pin MultiplexingMany serial/parallel port pins serve multiple fu

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-27Bits Name Description0:10 — Reserved11 PRSC PortResetS

MPC5200B Users Guide, Rev. 112-28 Freescale SemiconductorHost Control (HC) Operational Registers23 PPS PortPowerStatus (read)—bit reflects the port po

Host Control (HC) Operational RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 12-2929 PSS PortSuspendStatus (read)—bit indicates port is

Universal Serial Bus (USB)NotesMPC5200B Users Guide, Rev. 112-30 Freescale Semiconductor

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-1Chapter 13 BestComm13.1 OverviewThe following sections are contained in this document:

MPC5200B Users Guide, Rev. 113-2 Freescale SemiconductorFeatures summaryNOTEIt is possible for the BESTComm DMA to produce misaligned word addresses o

Task Table (Entry Table)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-3Each task has an entry (8 long words) that contains information about

MPC5200B Users Guide, Rev. 113-4 Freescale SemiconductorBestComm XLB Address Snooping13.14 BestComm XLB Address SnoopingBestComm prefetches data from

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-513.15.2 SDMA Current Pointer Register—MBAR + 0x1204 13.15.3

MPC5200B Users Guide, Rev. 113-6 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.5SDMA Interrupt Vector, PTD Control Register—MBAR + 0x

ArchitectureMPC5200B Users Guide, Rev. 1Freescale Semiconductor 1-9A Wake Up capability is supported by CAN, RTC, several GPIOs and the interrupt line

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-713.15.6 SDMA Interrupt Pending Register—MBAR + 0x1214 Bit Na

MPC5200B Users Guide, Rev. 113-8 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.7 SDMA Interrupt Mask Register—MBAR + 0x1218 Bit Name

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-913.15.8 SDMA Task Control 0 Register—MBAR + 0x121CSDMA Task

MPC5200B Users Guide, Rev. 113-10 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.9 SDMA Task Control 2 Register—MBAR + 0x1220SDMA Task

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-1113.15.10 SDMA Task Control 4 Register—MBAR + 0x1224SDMA Tas

MPC5200B Users Guide, Rev. 113-12 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.12 SDMA Task Control 8 Register—MBAR + 0x122CSDMA Tas

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-1313.15.14 SDMA Task Control C Register—MBAR + 0x1234SDMA Tas

MPC5200B Users Guide, Rev. 113-14 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.16 SDMA Initiator Priority 0 Register—MBAR + 0x123CSD

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-1513.15.17 SDMA Initiator Priority 4 Register—MBAR + 0x1240SD

MPC5200B Users Guide, Rev. 113-16 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.19 SDMA Initiator Priority 12 Register—MBAR + 0x1248S

MPC5200B Users Guide, Rev. 11-10 Freescale SemiconductorArchitecture

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-1713.15.20 SDMA Initiator Priority 16 Register—MBAR + 0x124CS

MPC5200B Users Guide, Rev. 113-18 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.21 SDMA Initiator Priority 20 Register—MBAR + 0x1250S

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-1913.15.23 SDMA Initiator Priority 28 Register—MBAR + 0x1258S

MPC5200B Users Guide, Rev. 113-20 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.24 SDMA Requestor MuxControl—MBAR + 0x125C 16:23 IPR3

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-21The remaining 16 Requestors are fixed as follows:12:13 Req2

MPC5200B Users Guide, Rev. 113-22 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.25 SDMA task Size0—MBAR + 0x1260SDMA task Size 1—MBAR

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-2313.15.26 SDMA task 0 & task Size 1 map 13.15.27 SDMA Re

MPC5200B Users Guide, Rev. 113-24 Freescale SemiconductorBestComm DMA Registers—MBAR+0x120013.15.28 SDMA Reserved Register 2—MBAR + 0x126C 13.15.29 SD

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-2513.15.31 SDMA Debug Module Control Register—MBAR + 0x1278 1

MPC5200B Users Guide, Rev. 113-26 Freescale SemiconductorBestComm DMA Registers—MBAR+0x1200The reserved encodings are set to 0 indicating an uninitial

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-1Chapter 2 Signal Descriptions2.1 OverviewThe MPC5200B contains a e300 core, an internal

BestComm DMA Registers—MBAR+0x1200MPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-27It must be noted that even if a breakpoint is issued at a s

MPC5200B Users Guide, Rev. 113-28 Freescale SemiconductorOn-Chip SRAM13.16 On-Chip SRAMMPC5200B contains 16KBytes of on-chip SRAM. This memory is dire

Programming ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-290451415192031Task 0Task Descriptor Start PointerTask Descriptor End PointerV

BestCommNotesMPC5200B Users Guide, Rev. 113-30 Freescale Semiconductor13.17.1.1 Integer ModeThis input signal is only valid if the pack signal is nega

Programming ModelMPC5200B Users Guide, Rev. 1Freescale Semiconductor 13-31task’s Variable Table is desired. In addition, if a task does not use the la

MPC5200B Users Guide, Rev. 113-32 Freescale SemiconductorProgramming Model

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-1Chapter 14 Fast Ethernet Controller (FEC)14.1 OverviewThe fast Ethernet controller (FE

MPC5200B Users Guide, Rev. 114-2 Freescale SemiconductorOverviewFigure 14-1. Block Diagram—FEC14.1.1 FeaturesThe FEC incorporates several features/des

Modes of OperationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-3• Automatic internal flushing of the Rx FIFO for runts (collision fragments)

MPC5200B Users Guide, Rev. 114-4 Freescale SemiconductorI/O Signal Overview14.3.1 Detailed Signal Descriptions14.3.1.1 MII Ethernet MAC-PHY InterfaceT

MPC5200B Users Guide, Rev. 12-2 Freescale SemiconductorOverviewFigure 2-1. 272-Pin PBGA Pin DetailTable 2-1 gives a list of MPC5200B I/O signals sorte

I/O Signal OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-5Tx_EN . . . . . . . . . . . . . Assertion of this signal indicates valid n

MPC5200B Users Guide, Rev. 114-6 Freescale SemiconductorFEC Memory Map and Registers14.3.1.2.1 MII Management Register SetThe MII management register

FEC Memory Map and RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-714.4.1 Control and Status (CSR) Memory MapTable 14-6. Module Memor

MPC5200B Users Guide, Rev. 114-8 Freescale SemiconductorFEC Memory Map and Registers14.4.2 MIB Block Counters Memory MapTable 14-8 defines the MIB Cou

FEC Memory Map and RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-9Table 14-8. MIB CountersAddress Mnemonic Description200 RMON_T_DRO

MPC5200B Users Guide, Rev. 114-10 Freescale SemiconductorFEC Registers—MBAR + 0x300014.5 FEC Registers—MBAR + 0x3000The FEC uses 37 32-bit registers.

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-1114.5.1 FEC ID Register—MBAR + 0x3000The read-only FEC ID Register

MPC5200B Users Guide, Rev. 114-12 Freescale SemiconductorFEC Registers—MBAR + 0x300014.5.2 FEC Interrupt Event Register—MBAR + 0x3004When an event occ

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-13R ReservedWBits Name Description0 HBERR Heartbeat Error— interrupt

MPC5200B Users Guide, Rev. 114-14 Freescale SemiconductorFEC Registers—MBAR + 0x300014.5.3 FEC Interrupt Enable Register—MBAR + 0x3008The IMASK regist

MPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-3Figure 2-2. 272-Pin PBGA — Top ViewA01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-15The R_DES_ACTIVE bit is cleared at reset and by the clearing of ET

MPC5200B Users Guide, Rev. 114-16 Freescale SemiconductorFEC Registers—MBAR + 0x300014.5.6 FEC Ethernet Control Register—MBAR + 0x3024The ECNTRL regis

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-1714.5.7 FEC MII Management Frame Register—MBAR + 0x3040This MII_DAT

MPC5200B Users Guide, Rev. 114-18 Freescale SemiconductorFEC Registers—MBAR + 0x3000user. When the write management frame operation is complete, the M

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-1914.5.9 FEC MIB Control Register—MBAR + 0x3064The MIB_CONTROL regis

MPC5200B Users Guide, Rev. 114-20 Freescale SemiconductorFEC Registers—MBAR + 0x300014.5.10 FEC Receive Control Register—MBAR + 0x3084The R_CNTRL regi

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-2114.5.11 FEC Hash Register—MBAR + 0x3088The read-only R_HASH regist

MPC5200B Users Guide, Rev. 114-22 Freescale SemiconductorFEC Registers—MBAR + 0x300014.5.13 FEC Physical Address Low Register—MBAR + 0x30E4The PADDR1

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-23Note: X: Bit is not reset and must be initialized.14.5.14 FEC Phy

MPC5200B Users Guide, Rev. 114-24 Freescale SemiconductorFEC Registers—MBAR + 0x3000Note: X: Bit is not reset and must be initialized.14.5.16 FEC Des

MPC5200B Users Guide, Rev. 12-4 Freescale SemiconductorPinout TablesFigure 2-3. MPC5200B Peripheral Muxing2.2 Pinout TablesTable 2-1. Signals by Ball/

FEC Registers—MBAR + 0x3000MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-25Note: X: Bit is not reset and must be initialized.14.5.18 FEC Des

MPC5200B Users Guide, Rev. 114-26 Freescale SemiconductorFEC Registers—MBAR + 0x3000Note: X: Bit is not reset and must be initialized.14.5.20 FEC Tx

FIFO InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-2714.6 FIFO InterfaceThe programming interface to the FIFO allows access to Data,

MPC5200B Users Guide, Rev. 114-28 Freescale SemiconductorFEC Tx FIFO Data Register—MBAR + 0x31A414.6.1 FEC Rx FIFO Data Register—MBAR + 0x318414.7 FEC

FEC Tx FIFO Status Register—MBAR + 0x31A8MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-2914.8.1 FEC Rx FIFO Control Register—MBAR + 0x318CFEC

MPC5200B Users Guide, Rev. 114-30 Freescale SemiconductorFEC Tx FIFO Status Register—MBAR + 0x31A8 14.8.2 FEC Rx FIFO Last Read Frame Pointer Register

FEC Tx FIFO Status Register—MBAR + 0x31A8MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-3114.8.3 FEC Rx FIFO Last Write Frame Pointer Register

MPC5200B Users Guide, Rev. 114-32 Freescale SemiconductorFEC Tx FIFO Status Register—MBAR + 0x31A8 14.8.5 FEC Rx FIFO Read Pointer Register—MBAR + 0x3

FEC Tx FIFO Status Register—MBAR + 0x31A8MPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-3314.8.6 FEC Rx FIFO Write Pointer Register—MBAR + 0x3

MPC5200B Users Guide, Rev. 114-34 Freescale SemiconductorInitialization Sequence14.8.8 FEC Transmit FSM Register—MBAR + 0x31C8The transmit finite stat

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-4 Freescale Semiconductor7.3.2.1.16 GPS GPIO Simple Interrupt Status Regis

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-5A11 PSC1_1 C06 PSC3_3A12 PSC6_2 C07 PSC3_0A13 PORRESET C08 CORE_PLL_AVDDA14 SRESET

Initialization SequenceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-3514.9.2 User Initialization (Prior to Asserting ETHER_EN)The user needs

MPC5200B Users Guide, Rev. 114-36 Freescale SemiconductorInitialization Sequence14.9.3.2 Transmit Frame Control WordThe only requirement for this cont

Initialization SequenceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-37Bits 31-27, 24-0—Reserved14.9.4 Network Interface OptionsThe FEC suppo

MPC5200B Users Guide, Rev. 114-38 Freescale SemiconductorInitialization SequenceIn MII mode the receiver checks for at least one byte matching the SFD

Initialization SequenceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-39Figure 14-2. Ethernet Address Recognition - receive block decisionsAcc

MPC5200B Users Guide, Rev. 114-40 Freescale SemiconductorInitialization SequenceThe hash table algorithm used in the group and individual hash filteri

Initialization SequenceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-41Table 14-45. Destination Address to 6-Bit Hash48-bit DA 6-bit hash (in

MPC5200B Users Guide, Rev. 114-42 Freescale SemiconductorInitialization Sequence14.9.7 Full-Duplex Flow ControlFull-duplex flow control allows the use

Initialization SequenceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-43Pause frame detection is performed by the receiver and microcontroller

MPC5200B Users Guide, Rev. 114-44 Freescale SemiconductorInitialization SequenceIf a collision occurs within 64 byte times the retry process is initia

MPC5200B Users Guide, Rev. 12-6 Freescale SemiconductorPinout TablesE01 TIMER_7 J10 VSS_IO/COREE02 TIMER_6 J11 VSS_IO/COREE03 TIMER_5 J12 VSS_IO/COREE

Initialization SequenceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 14-45Non-Octet Error (Dribbling Bits) — The Ethernet controller handles up

Fast Ethernet Controller (FEC)NotesMPC5200B Users Guide, Rev. 114-46 Freescale Semiconductor

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-1Chapter 15 Programmable Serial Controller (PSC)15.1 OverviewThe following sections are

MPC5200B Users Guide, Rev. 115-2 Freescale SemiconductorOverview15.1.1 PSC Functions OverviewThe PSC module of the MPC5200 provide different groups of

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-3PSC detect a “codec not ready” status the PSC will stop sending and receiving data. In

MPC5200B Users Guide, Rev. 115-4 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00• Selectable pulse width: e

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-5PSC module operation is con

MPC5200B Users Guide, Rev. 115-6 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00Table 15-4. Mode Register 1

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-715.2.2 Mode Register 2 (0x0

MPC5200B Users Guide, Rev. 115-8 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.3 Status Register (0x0

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-7M09 VSS_IO/CORE T18 MEM_MDQ_30M10 VSS_IO/CORE T19 MEM_MDQ_3M11 VSS_IO/CORE T20 MEM

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-9Table 15-12. Status Registe

MPC5200B Users Guide, Rev. 115-10 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C003 ORERR Overrun ErrorIndic

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-11NOTEThe FIFO related statu

MPC5200B Users Guide, Rev. 115-12 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.4 Clock Select Regist

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-13Table 15-16. Command Regis

MPC5200B Users Guide, Rev. 115-14 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C004:5 00 no actiontakenCause

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-1515.2.6 Rx Buffer Register

MPC5200B Users Guide, Rev. 115-16 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.7 Tx Buffer Register

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-1715.2.8 Input Port Change R

MPC5200B Users Guide, Rev. 115-18 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.9 Auxiliary Control R

MPC5200B Users Guide, Rev. 12-8 Freescale SemiconductorPinout TablesV13 EXT_AD_0 Y10 EXT_AD_10V14 LP_ALE Y11 EXT_AD_7V15 LP_CS2 Y12 EXT_AD_3V16 LP_CS5

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-1915.2.10 Interrupt Status R

MPC5200B Users Guide, Rev. 115-20 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.11 Interrupt Mask Reg

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-21 Table 15-28. Interrupt M

MPC5200B Users Guide, Rev. 115-22 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.12 Counter Timer Uppe

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-2315.2.13 Counter Timer Lowe

MPC5200B Users Guide, Rev. 115-24 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00R FrameSyncDiv[0:7] BitClk

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-25The Mclk frequency is gene

MPC5200B Users Guide, Rev. 115-26 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.15 AC97 Slots Registe

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-2715.2.17 AC97 Status Data R

MPC5200B Users Guide, Rev. 115-28 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.19 Input Port Regist

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-9Table 2-2. Signals by Signal NameSignal Name Ball/Pin Signal Name Ball/PinATA_DACK

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-2915.2.20 Output Port 1 Bit

MPC5200B Users Guide, Rev. 115-30 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.22 Serial Interface C

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-313 SHDIR Codec—Shift Direct

MPC5200B Users Guide, Rev. 115-32 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0013 Cell2xClk Codec —Cell S

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-3315.2.23 Infrared Control 1

MPC5200B Users Guide, Rev. 115-34 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.25 Infrared SIR Divid

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-3515.2.26 Infrared MIR Divid

MPC5200B Users Guide, Rev. 115-36 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 15.2.27 Infrared FIR Divi

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-37Bit Name Description0:3 —

MPC5200B Users Guide, Rev. 115-38 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.28 Rx FIFO Number of

MPC5200B Users Guide, Rev. 12-10 Freescale SemiconductorPinout TablesEXT_AD_4 V11 PSC6_0 B12EXT_AD_5 W12 PSC6_2 A12PSC6_3 C13 MEM_MBA_1 A17PSC6_1 C11

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-3915.2.32 Rx FIFO Control (0

MPC5200B Users Guide, Rev. 115-40 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.34 Rx FIFO Read Point

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-4115.2.37 Rx FIFO Last Write

MPC5200B Users Guide, Rev. 115-42 Freescale SemiconductorPSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C0015.2.40 Tx FIFO Control (0

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-4315.2.43 Tx FIFO Write Poin

MPC5200B Users Guide, Rev. 115-44 Freescale SemiconductorPSC Operation Modes15.3 PSC Operation ModesThis section describes the different PSC operation

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-45Figure 1-1PSC UART Block DiagramAn internal interrupt request signal (IRQ)

MPC5200B Users Guide, Rev. 115-46 Freescale SemiconductorPSC Operation ModesFigure 15-2. Signal configuration for a PSC/RS-232 interface15.3.1.2 UART

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-47After the stop bits are sent, if no new character is in the Tx holding reg

MPC5200B Users Guide, Rev. 115-48 Freescale SemiconductorPSC Operation ModesFigure 15-5. Timing Diagram—ReceiverWhen the receiver detects a high-to-lo

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-11MEM_MA_10 B17 MEM_MDQS_0 N20MEM_MA_11 E20 MEM_MDQS_1 H20MEM_MA_12 F19 MEM_MDQS_2

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-4915.3.2 PSC in Codec ModeAfter reset all PSCs are in UART mode. PSC1,2,3 an

MPC5200B Users Guide, Rev. 115-50 Freescale SemiconductorPSC Operation Modes15.3.2.1 Block Diagram and Signal Definition for Codec ModeFigure 15-6. PS

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-5115.3.2.2 Codec Clock and FrameSync GenerationThe serial BitClk and the Fra

MPC5200B Users Guide, Rev. 115-52 Freescale SemiconductorPSC Operation ModesThe source for the internal clock generation is the MclkDiv clock divider

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-53• Data shift direction SICR[SHDIR], data shifted out LSB first if SICR[SHD

MPC5200B Users Guide, Rev. 115-54 Freescale SemiconductorPSC Operation Modes• FrameSync is low true• lsb first, transfer starts one cycle after the le

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-55Figure 15-10. ESAI Data TransmissionTable 15-80 shows an example how to co

MPC5200B Users Guide, Rev. 115-56 Freescale SemiconductorPSC Operation Modes15.3.2.5 Transmitting and Receiving in “Cell Phone” ModeThe transmission p

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-5715.3.2.6 Transmitting and Receiving in I2S Master ModeThe next support mod

MPC5200B Users Guide, Rev. 115-58 Freescale SemiconductorPSC Operation ModesFigure 15-12. I2S-Data TransmissionTable 15-84 shows an example how to con

MPC5200B Users Guide, Rev. 12-12 Freescale SemiconductorPinout TablesPSC2_4 A08 USB_6 G04PSC3_0 C07 USB_7 F01PSC3_1 B07 USB_8 F02PSC3_2 A07 USB_9 F03P

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-5915.3.2.7 Transmitting and Receiving in SPI ModeAn other available Codec mo

MPC5200B Users Guide, Rev. 115-60 Freescale SemiconductorPSC Operation ModesFigure 15-13. SPI ParameterTable 15-85 shows an example how to configure t

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-61Table 15-86 shows an example how to configure the PSC2 as SPI slave.• use

MPC5200B Users Guide, Rev. 115-62 Freescale SemiconductorPSC Operation Modes15.3.3.1 Block Diagram and Signal Definition for AC97 ModeFigure 15-14. PS

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-63Figure 15-15. PSC - AC97 InterfaceFigure 15-16 shows the Timing diagram fo

MPC5200B Users Guide, Rev. 115-64 Freescale SemiconductorPSC Operation ModesLow-power mode can be left through either a warm or cold reset. The CPU do

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-65the slot request for the specified slots was active (slot request bit was

MPC5200B Users Guide, Rev. 115-66 Freescale SemiconductorPSC Operation ModesTable 15-90. Signal Description for IrDa ModeFigure 15-17. PSC SIR Block D

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-6715.3.4.1.3 Configuration Sequence Example for SIR ModeThe Table 15-91 show

MPC5200B Users Guide, Rev. 115-68 Freescale SemiconductorPSC Operation ModesFigure 15-19. PSC MIR and FIR Block DiagramFor MIR and FIR mode the clock

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-13VDD_MEM_IO P17VDD_MEM_IO T17VSS_IO/CORE D04VSS_IO/CORE D16VSS_IO/CORE J09VSS_IO/C

PSC Operation ModesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-69The STA represents the start of the frame and the STO represents the end o

Programmable Serial Controller (PSC)NotesMPC5200B Users Guide, Rev. 115-70 Freescale Semiconductor15.3.4.3 PSC in FIR ModeThe FIR mode is also a suppo

PSC FIFO SystemMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-71NOTEThe FIR module doesn’t support the CRC generation. If the transfer require

MPC5200B Users Guide, Rev. 115-72 Freescale SemiconductorPSC FIFO SystemDepending on whether the FIFO is set for Tx or Rx, “Alarm” and “Granularity” a

PSC FIFO SystemMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-73Figure 15-22. PSC FIFO System15.4.1 RX FIFOThe RX FIFO space is 512 Byte. For

MPC5200B Users Guide, Rev. 115-74 Freescale SemiconductorPSC FIFO SystemWhen using BestComm you must specify a non-zero “Granularity” to get FIFO unde

PSC FIFO SystemMPC5200B Users Guide, Rev. 1Freescale Semiconductor 15-75Figure 15-24. Local Loop-BackFeatures of this local loop-back mode are:• Trans

MPC5200B Users Guide, Rev. 115-76 Freescale SemiconductorPSC FIFO SystemFigure 15-26. Timing Diagram—Multidrop ModeA character sent from the master st

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 16-1Chapter 16 XLB Arbiter16.1 OverviewThis document contains the following section:• Sect

MPC5200B Users Guide, Rev. 116-2 Freescale SemiconductorOverviewMultiple masters at level 0 will only be able to perform one tenure before the bus is

MPC5200B Users Guide, Rev. 12-14 Freescale SemiconductorPinout TablesTable 2-4. LocalPlus Pin FunctionsPin name BALLLocalPlusNon-muxLocalPlusMULTIPLEX

XLB Arbiter Registers—MBAR + 0x1F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 16-316.1.1.4.2 Other Tenure Ending ConditionsIn addition to the

MPC5200B Users Guide, Rev. 116-4 Freescale SemiconductorXLB Arbiter Registers—MBAR + 0x1F00Table 16-1. Arbiter Configuration Registermsb 0 1 2 3 4 5 6

XLB Arbiter Registers—MBAR + 0x1F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 16-5NOTEThe PLDIS reset value is 1, which means the XLB Arbiter

MPC5200B Users Guide, Rev. 116-6 Freescale SemiconductorXLB Arbiter Registers—MBAR + 0x1F0016.2.4 Arbiter Interrupt Enable Register (R/W)—MBAR + 0x1F4

XLB Arbiter Registers—MBAR + 0x1F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 16-716.2.5 Arbiter Address Capture Register (R)—MBAR + 0x1F50Th

MPC5200B Users Guide, Rev. 116-8 Freescale SemiconductorXLB Arbiter Registers—MBAR + 0x1F0016.2.6 Arbiter Bus Signal Capture Register (R)—MBAR + 0x1F5

XLB Arbiter Registers—MBAR + 0x1F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 16-916.2.8 Arbiter Data Tenure Time-Out Register (R/W)—MBAR + 0

MPC5200B Users Guide, Rev. 116-10 Freescale SemiconductorXLB Arbiter Registers—MBAR + 0x1F0016.2.10 Arbiter Master Priority Enable Register (R/W)—MBAR

XLB Arbiter Registers—MBAR + 0x1F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 16-1116.2.11 Arbiter Master Priority Register (R/W)—MBAR + 0x1F

MPC5200B Users Guide, Rev. 116-12 Freescale SemiconductorXLB Arbiter Registers—MBAR + 0x1F0016.2.12Arbiter Snoop Window Register (RW)—MBAR + 0x1F70The

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-58.4.4.3 Bank Active Command ...

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-15PCI_CBE_2 W06 PCI_CBE_2 A3 A19PCI_CBE_3 Y02 PCI_CBE_3 A4 A20PCI_TRDY W05 PCI_TRDY

XLB Arbiter Registers—MBAR + 0x1F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 16-1316.2.13Arbiter Reserved Registers—MBAR + 0x1F00-1F3C, 0x1F

XLB ArbiterNotesMPC5200B Users Guide, Rev. 116-14 Freescale Semiconductor

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-1Chapter 17 Serial Peripheral Interface (SPI)17.1 OverviewThe following sections are co

MPC5200B Users Guide, Rev. 117-2 Freescale SemiconductorSPI Signal Description17.1.2 Modes of OperationThe SPI functions in the following three modes:

SPI Registers—MBAR + 0x0F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-3The SS pin is the mode fault input when the SPI is in master mode a

MPC5200B Users Guide, Rev. 117-4 Freescale SemiconductorSPI Registers—MBAR + 0x0F0017.3.2 SPI Control Register 2—MBAR + 0x0F01 6 SSOE Slave Select (SS

SPI Registers—MBAR + 0x0F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-517.3.3 SPI Baud Rate Register—MBAR + 0x0F04 The SPI baud rate is de

MPC5200B Users Guide, Rev. 117-6 Freescale SemiconductorSPI Registers—MBAR + 0x0F0017.3.4 SPI Status Register —MBAR + 0x0F05 Table 17-7. SPI Baud Rate

SPI Registers—MBAR + 0x0F00MPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-717.3.5 SPI Data Register—MBAR + 0x0F09 17.3.6 SPI Port Data Registe

MPC5200B Users Guide, Rev. 117-8 Freescale SemiconductorFunctional Description17.4 Functional Description17.4.1 GeneralThe SPI module allows full-dupl

MPC5200B Users Guide, Rev. 12-16 Freescale SemiconductorPinout Tables1. The PCI signals, which are not used as address in Large Flash mode, are drive

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-9The SS pin is normally an input which should remain in the inactive high

MPC5200B Users Guide, Rev. 117-10 Freescale SemiconductorFunctional DescriptionFigure 17-2. Master/Slave Transfer Block Diagram17.4.4.1 Clock Phase an

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-11Figure 17-3. SPI Clock Format 0 (CPHA = 0)In slave mode, if the SS line

MPC5200B Users Guide, Rev. 117-12 Freescale SemiconductorFunctional Descriptionsignal is the output from the master. The SS line is the slave select i

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-13Figure 17-5. Baud Rate Divisor Equation17.4.6 Special Features17.4.6.1

MPC5200B Users Guide, Rev. 117-14 Freescale SemiconductorFunctional Description17.4.7 Error ConditionsThe SPI has two error conditions:• Write collisi

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 17-15NOTECare must be taken when expecting data from a master while the slav

MPC5200B Users Guide, Rev. 117-16 Freescale SemiconductorFunctional Description

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-1Chapter 18 Inter-Integrated Circuit (I2C)18.1 OverviewThe following sections are conta

MPC5200B Users Guide, Rev. 118-2 Freescale SemiconductorI2C ControllerFigure 18-1. Block Diagram—I2C Module18.2 I2C ControllerThe I2C has simple bidir

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-17Pin EXT_AD_30 Ball R03LocalPlus Bus multiplexed mode Address Phase

I2C ControllerMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-3The master terminates communication by generating a STOP signal, which frees the

MPC5200B Users Guide, Rev. 118-4 Freescale SemiconductorI2C ControllerFigure 18-4. Timing Diagram—Receiver Acknowledgement18.2.2.4 Repeated StartA rep

I2C Interface RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-5Figure 18-6. Timing Diagram—Clock SynchronizationA data arbitration pro

MPC5200B Users Guide, Rev. 118-6 Freescale SemiconductorI2C Interface Registers18.3.1 I2C Address Register (MADR)—MBAR + 0x3D00 / 0x3D40 18.3.2 I2C Fr

I2C Interface RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-7Timing Diagram—SCL Period and SDA Hold TimeFigure 18-8. Timing Diagram

MPC5200B Users Guide, Rev. 118-8 Freescale SemiconductorI2C Interface Registers1. Identify all rows of Table 18-4 where SCL Period satisfies criteria

I2C Interface RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-900 000 011 144 25 70 7300 000 100 288 49 142 14500 000 101 576 97 286 2

MPC5200B Users Guide, Rev. 118-10 Freescale SemiconductorI2C Interface Registers00 101 110 768 65 382 38500 101 111 1536 129 766 76900 110 000 24 8 8

I2C Interface RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-1101 011 001 136 26 60 7001 011 010 256 42 116 13001 011 011 480 66 236

MPC5200B Users Guide, Rev. 118-12 Freescale SemiconductorI2C Interface Registers10 or 11 000 100 1152 196 568 58010 or 11 000 101 2304 388 1144 115610

MPC5200B Users Guide, Rev. 12-18 Freescale SemiconductorPinout TablesPin EXT_AD_27 Ball Y01LocalPlus Bus multiplexed mode Address Phase

I2C Interface RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-1318.3.3 I2C Control Register (MCR)—MBAR + 0x3D08 / 0x3D48 10 or 11 101

MPC5200B Users Guide, Rev. 118-14 Freescale SemiconductorI2C Interface RegistersBit Name Description0ENI2C Enable—bit controls software reset of entir

I2C Interface RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-1518.3.4 I2C Status Register (MSR)—MBAR + 0x3D0C / 0x3D4C Table 18-6. I2

MPC5200B Users Guide, Rev. 118-16 Freescale SemiconductorI2C Interface Registers18.3.5 I2C Data I/O Register (MDR)—MBAR+ x3D10 / 0x3D50 5 SRW Slave Re

I2C Interface RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-1718.3.6 I2C Interrupt Control Register—MBAR + 0x3D20 The Interrupt Cont

MPC5200B Users Guide, Rev. 118-18 Freescale SemiconductorI2C Interface Registers• To the RX requestor at SDMA, if RE is set to 1.Typically, only one (

Initialization SequenceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-19An I2C glitch filter has been added outside the I2C legacy modules (bu

MPC5200B Users Guide, Rev. 118-20 Freescale SemiconductorTransfer Initiation and Interrupt18.5.3 Special Note on AKFA new status bit has been added to

Transfer Initiation and InterruptMPC5200B Users Guide, Rev. 1Freescale Semiconductor 18-21Figure 18-9. Software Flowchart of Typical I2C Interrupt Rou

MPC5200B Users Guide, Rev. 118-22 Freescale SemiconductorTransfer Initiation and Interrupt

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-19Pin EXT_AD_24 Ball U03LocalPlus Bus multiplexed mode Address Phase

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-1Chapter 19 Controller Area Network ( MSCAN )19.1 OverviewThe following sections are co

MPC5200B Users Guide, Rev. 119-2 Freescale SemiconductorFeatures19.2 FeaturesThe basic features of the MSCAN are as follows:• Implementation of the CA

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-3Figure 19-2. The CAN System19.5 Memory Map / Register Definiti

MPC5200B Users Guide, Rev. 119-4 Freescale SemiconductorMemory Map / Register DefinitionTable 19-1 shows the individual registers associated with the

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-519.5.2 Register DescriptionsThis section describes in detail a

MPC5200B Users Guide, Rev. 119-6 Freescale SemiconductorMemory Map / Register DefinitionBit Name Description0 RXFRM Received Frame—flag bit is read an

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-719.5.4 MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 / 0x98

MPC5200B Users Guide, Rev. 119-8 Freescale SemiconductorMemory Map / Register Definition19.5.5 MSCAN Bus Timing Register 0 (CANBTR0)—MBAR + 0x0904 / 0

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-919.5.6 MSCAN Bus Timing Register 1 (CANBTR1)—MBAR + 0x0905 / 0

MPC5200B Users Guide, Rev. 119-10 Freescale SemiconductorMemory Map / Register Definition19.5.7 MSCAN Receiver Flag Register (CANRFLG)—MBAR+0x0908 / 0

MPC5200B Users Guide, Rev. 12-20 Freescale SemiconductorPinout TablesPin EXT_AD_21 Ball Y03LocalPlus Bus multiplexed mode Address Phase

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-11Bit Name Description0 WUPIF WakeUp Interrupt Flag—If MSCAN de

MPC5200B Users Guide, Rev. 119-12 Freescale SemiconductorMemory Map / Register Definition19.5.8 MSCAN Receiver Interrupt Enable Register (CANRIER)—MBA

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-13Note: The MSCAN Receive Interrupt Enable Register is held in

MPC5200B Users Guide, Rev. 119-14 Freescale SemiconductorMemory Map / Register Definition19.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-1519.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)—MBAR +0

MPC5200B Users Guide, Rev. 119-16 Freescale SemiconductorMemory Map / Register Definition19.5.14 MSCAN ID Acceptance Control Register (CANIDAC)—MBAR +

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-1719.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR

MPC5200B Users Guide, Rev. 119-18 Freescale SemiconductorMemory Map / Register Definition19.5.17 MSCAN ID Acceptance Registers (CANIDAR0-7)—MBAR + 0x0

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-19 READ: AnytimeWRITE: Anytime in initialization mode (INITRQ +

MPC5200B Users Guide, Rev. 119-20 Freescale SemiconductorMemory Map / Register Definition19.5.18 MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0x0928 / 0

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-21Pin EXT_AD_18 Ball V04LocalPlus Bus multiplexed mode Address Phase

Memory Map / Register DefinitionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-21 READ: AnytimeWRITE: Anytime in initialization mode (INITRQ +

MPC5200B Users Guide, Rev. 119-22 Freescale SemiconductorProgrammer’s Model of Message Storage— CANIDMR719.6 Programmer’s Model of Message StorageThe

Programmer’s Model of Message StorageMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-23Read: anytime for transmit buffers; only when RXF flag i

MPC5200B Users Guide, Rev. 119-24 Freescale SemiconductorProgrammer’s Model of Message Storage19.6.1 Identifier Registers (IDR0-3)The identifier regis

Programmer’s Model of Message StorageMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-2519.6.3 Data Length Register (DLR)This register keeps the

MPC5200B Users Guide, Rev. 119-26 Freescale SemiconductorFunctional Description19.6.5 MSCAN Time Stamp Register High (TSRH)—MBAR + 0x097C / 0x09FC REA

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-2719.7.2 Message StorageFigure 19-3. User Model for Message Buffer Organi

MPC5200B Users Guide, Rev. 119-28 Freescale SemiconductorFunctional DescriptionA double buffer scheme de-couples the reloading of the transmit buffer

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-29flag, and generates a receive interrupt Section 19.7.9.2, Receive Inter

MPC5200B Users Guide, Rev. 119-30 Freescale SemiconductorFunctional DescriptionFigure 19-4. 32-bit Maskable Identifier Acceptance FilterFigure 19-5. 1

MPC5200B Users Guide, Rev. 12-22 Freescale SemiconductorPinout TablesPin EXT_AD_15 Ball U08LocalPlus Bus multiplexed mode Address Phase 8

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-31Figure 19-6. 8-bit Maskable Identifier Acceptance Filters19.7.4 Protoco

MPC5200B Users Guide, Rev. 119-32 Freescale SemiconductorFunctional Description• All registers which control the configuration of the MSCAN cannot be

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-33• Time Segment 2: This segment represents the PHASE_SEG2 of the CAN sta

MPC5200B Users Guide, Rev. 119-34 Freescale SemiconductorFunctional Description19.7.6 Timer LinkThe MSCAN generates an internal time stamp whenever a

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-3519.7.8.1 CPU Run ModeAs can be seen in Table 19-35, only MSCAN Sleep Mo

MPC5200B Users Guide, Rev. 119-36 Freescale SemiconductorFunctional DescriptionNOTEThe MCU cannot clear the SLPRQ bit before Sleep Mode (SLPRQ=1 and S

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-37Figure 19-11. Initialization Request/Acknowledge CycleDue to independen

Controller Area Network ( MSCAN )NotesMPC5200B Users Guide, Rev. 119-38 Freescale Semiconductor19.7.9.1 Transmit InterruptAt least one of the three tr

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 19-3919.7.9.4 Error InterruptAn overrun of the receiver FIFO, error, warnin

MPC5200B Users Guide, Rev. 119-40 Freescale SemiconductorFunctional Description

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-23Pin EXT_AD_12 Ball Y09LocalPlus Bus multiplexed mode Address Phase

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-1Chapter 20 Byte Data Link Controller (BDLC)20.1 OverviewThe BDLC module is a serial co

MPC5200B Users Guide, Rev. 120-2 Freescale SemiconductorModes of OperationFigure 20-1. BDLC Operating Modes State Diagram• Power OffThis mode is enter

Modes of OperationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-3•RunThis mode is entered from the BDLC Disabled mode when the BDLCE bit in t

MPC5200B Users Guide, Rev. 120-4 Freescale SemiconductorBlock Diagram• Low Power OptionsThe BDLC module can save power in Disabled, Wait, and Stop mod

Signal DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-5and reception. The MUX Interface provides the link between the BDLC digital

MPC5200B Users Guide, Rev. 120-6 Freescale SemiconductorMemory Map and RegistersREAD: any timeWRITE: IMSG, IE, and WCM any time. CLKS write once in no

Memory Map and RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-71 = Stop BDLC internal clocks during CPU wait mode (BDLC_STOP)0 = Run

MPC5200B Users Guide, Rev. 120-8 Freescale SemiconductorMemory Map and RegistersIf the CPU executes a STOP all clocks to the BDLC as well as the clock

Memory Map and RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-90 = When cleared, digital filter input is connected to receive pin (RX

MPC5200B Users Guide, Rev. 120-10 Freescale SemiconductorMemory Map and RegistersThe BDLC supports the In-frame Response (IFR) feature of J1850 by set

MPC5200B Users Guide, Rev. 12-24 Freescale SemiconductorPinout TablesPin EXT_AD_9 Ball V10LocalPlus Bus multiplexed mode Address Phase

Memory Map and RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-11After the byte in the BDLC Data Register has been loaded into the tra

MPC5200B Users Guide, Rev. 120-12 Freescale SemiconductorMemory Map and RegistersNOTEThe extra logic 1s are an enhancement to the J1850 protocol which

Memory Map and RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-13READ: any timeWRITE: write once in normal and emulation modes.Registe

MPC5200B Users Guide, Rev. 120-14 Freescale SemiconductorMemory Map and Registers20.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309This regi

Memory Map and RegistersMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-1520.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130CThe following

MPC5200B Users Guide, Rev. 120-16 Freescale SemiconductorFunctional DescriptionREAD: any timeWRITE: ignored in normal and emulation modesRegister func

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-17Messages transmitted by the BDLC module onto the J1850 bus must contain

MPC5200B Users Guide, Rev. 120-18 Freescale SemiconductorFunctional Description Figure 20-5. J1850 VPW SymbolsEach message will begin with an SOF symb

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-19The SOF symbol is defined as passive to active transition followed by a

MPC5200B Users Guide, Rev. 120-20 Freescale SemiconductorFunctional Description5 Start of Frame (SOF) Ttva3198 200 202 tbdlc6 End of Data (EOD)1Ttvp31

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-6 Freescale Semiconductor9.7.4.4 LPC Rx/Tx FIFO Alarm Register—MBAR + 0x3C

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-25Pin EXT_AD_6 Ball U11LocalPlus Bus multiplexed mode Address Phase

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-21Table 20-16. BDLC Receiver VPW Symbol Timing for Binary FrequenciesNumb

MPC5200B Users Guide, Rev. 120-22 Freescale SemiconductorFunctional DescriptionThe min and max symbol limits shown in the following sections (Invalid

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-23Figure 20-7. J1850 VPW EOF and IFS Symbols• Valid EOF & IFS SymbolI

MPC5200B Users Guide, Rev. 120-24 Freescale SemiconductorFunctional DescriptionFigure 20-8. J1850 VPW Active Symbols• Invalid Active BitIf the active

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-25• Valid BREAK SymbolIf the next active to passive transition does not o

MPC5200B Users Guide, Rev. 120-26 Freescale SemiconductorFunctional Description20.8.1.4 J1850 Bus ErrorsThe BDLC module detects several types of trans

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-27If a BREAK symbol is received while the BDLC module is transmitting or

MPC5200B Users Guide, Rev. 120-28 Freescale SemiconductorFunctional DescriptionFigure 20-11. BDLC Module Rx Digital Filter Block Diagram• OperationThe

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-2920.8.3.1 Protocol ArchitectureThe Protocol Handler contains the State M

MPC5200B Users Guide, Rev. 120-30 Freescale SemiconductorFunctional Description• Digital Loopback MultiplexerThe Digital Loopback Multiplexer connects

MPC5200B Users Guide, Rev. 12-26 Freescale SemiconductorPinout TablesPin EXT_AD_3 Ball Y12LocalPlus Bus multiplexed mode Address Phase

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-31NOTEDue to the byte-level architecture of the BDLC module, the 12-byte

MPC5200B Users Guide, Rev. 120-32 Freescale SemiconductorFunctional DescriptionSimilar to a loss of arbitration, if any error (except a CRC error) is

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-33Figure 20-13. Basic BDLC Transmit Flowchart20.8.5 Receiving A Message T

MPC5200B Users Guide, Rev. 120-34 Freescale SemiconductorFunctional Description20.8.5.1 BDLC Reception Control BitsThe only control bit which is used

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-35Once a message byte has been received, the CPU must service the BDLC Da

MPC5200B Users Guide, Rev. 120-36 Freescale SemiconductorFunctional DescriptionFigure 20-14. Basic BDLC Receive Flowchart20.8.6 Transmitting An In-Fra

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-3720.8.6.1 IFR Types Supported by the BDLC moduleSAE J1850 defines four d

MPC5200B Users Guide, Rev. 120-38 Freescale SemiconductorFunctional Description20.8.6.3 Transmit Single Byte IFRThe Transmit Single Byte IFR (TSIFR) b

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-39• Transmitting a Type 1 IFRTo transmit a Type 1 IFR, the user loads the

MPC5200B Users Guide, Rev. 120-40 Freescale SemiconductorFunctional Description— Step 1: Load the IFR Byte into the BDLC Data RegisterAs with the Type

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-27Pin EXT_AD_0 Ball V13LocalPlus Bus multiplexed mode Address Phase

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-41byte when TEOD is set, the BDLC module will continue the transmission u

MPC5200B Users Guide, Rev. 120-42 Freescale SemiconductorFunctional DescriptionThe user begins initiation of a Type 3 IFR, as with each of the other I

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-43Figure 20-17. Transmitting A Type 3 IFR20.8.7 Receiving An In-Frame Res

MPC5200B Users Guide, Rev. 120-44 Freescale SemiconductorFunctional DescriptionNOTEAs with a message transmission, the IMSG bit should never be used t

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-45.Figure 20-18. Receiving An IFR With the BDLC module20.8.7.2 Receiving

MPC5200B Users Guide, Rev. 120-46 Freescale SemiconductorFunctional DescriptionBecause of the BDLC module’s architecture, it can both transmit and rec

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-47Figure 20-19. Basic BDLC Module Transmit Flowchart20.8.9 BDLC Module In

MPC5200B Users Guide, Rev. 120-48 Freescale SemiconductorFunctional Description20.8.9.2 Initializing the Configuration BitsThe first step necessary fo

Functional DescriptionMPC5200B Users Guide, Rev. 1Freescale Semiconductor 20-49time passes between the exit from loopback modes and enabling the BDLC

MPC5200B Users Guide, Rev. 120-50 Freescale SemiconductorResets20.9 Resets20.9.1 GeneralThe reset state of each individual bit is listed within Sectio

MPC5200B Users Guide, Rev. 12-28 Freescale SemiconductorPinout TablesPin PCI_TRDY Ball W05PCI PCI_TRDY logic 1 PCI_TRDYPCI Target ReadyLFLAS

OverviewMPC5200B Users Guide, Rev. 1Freescale Semiconductor 21-1Chapter 21 Debug Support and JTAG Interface21.1 OverviewThe following sections are con

MPC5200B Users Guide, Rev. 121-2 Freescale SemiconductorTAP Link Module (TLM) and Slave TAP ImplementationFigure 21-1. Generic TLM/TAP Architecture Di

TAP Link Module (TLM) and Slave TAP ImplementationMPC5200B Users Guide, Rev. 1Freescale Semiconductor 21-3Figure 21-2. Generic TAP Link Module (TLM) D

MPC5200B Users Guide, Rev. 121-4 Freescale SemiconductorTLM and TAP Signal DescriptionsFigure 21-3. Generic Slave TAP21.3 TLM and TAP Signal Descripti

Slave Test Reset (STRST)MPC5200B Users Guide, Rev. 1Freescale Semiconductor 21-521.3.5 Test Data Out (TDO)Serial test data output is routed from the a

MPC5200B Users Guide, Rev. 121-6 Freescale Semiconductore300 Core JTAG/COP Serial InterfaceFigure 21-4. State Diagram—TAP ControllerInstructions are l

TLM Link DR InstructionsMPC5200B Users Guide, Rev. 1Freescale Semiconductor 21-7Figure 21-5. e300 Core JTAG/COP Serial Interface21.7 TLM Link DR Instr

MPC5200B Users Guide, Rev. 121-8 Freescale SemiconductorTLM Test Instructions21.7.1 TLM:TLMENAThe TLM:TLMENA pseudo-instruction selects the 6-bit TLM

e300 COP/BDM InterfaceMPC5200B Users Guide, Rev. 1Freescale Semiconductor 21-9Preload: To shift an initial value into the boundary scan register prior

Debug Support and JTAG InterfaceNotesMPC5200B Users Guide, Rev. 121-10 Freescale Semiconductor

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-29Pin PCI_RESET Ball R02PCI PCI_RESET logic 0 PCI Reset Output (open drai

AMPC5200B Users Guide, Rev. 1Freescale Semiconductor A-1Appendix AAcronyms and TermsThis section contains an alphabetical list of terms, phrases, acro

MPC5200B Users Guide, Rev. 1A-2 Freescale SemiconductorCBIP . . . . . . . . . . . . . . . . . . . . Bit Interleaved ParityBIST . . . . . . . . . . .

DMPC5200B Users Guide, Rev. 1Freescale Semiconductor A-3Context synchronization . . . . An operation that ensures:• all instructions in execution comp

MPC5200B Users Guide, Rev. 1A-4 Freescale SemiconductorEEEA . . . . . . . . . . . . . . . . . . . . . Effective Address—The 32- or 64-bit address spec

HMPC5200B Users Guide, Rev. 1Freescale Semiconductor A-5HHarvard architecture . . . . . . . An architectural model featuring separate caches for instr

MPC5200B Users Guide, Rev. 1A-6 Freescale SemiconductorJJJAVA™ . . . . . . . . . . . . . . . . . From Sun Microsystems, Inc.—a robust and versatile pr

NMPC5200B Users Guide, Rev. 1Freescale Semiconductor A-7MAC/PHY . . . . . . . . . . . . . . Multiply-and-ACcumulate/Physical Layer DeviceMaster . . .

MPC5200B Users Guide, Rev. 1A-8 Freescale SemiconductorOOOC. . . . . . . . . . . . . . . . . . . . . Output CompareOE . . . . . . . . . . . . . . . .

QMPC5200B Users Guide, Rev. 1Freescale Semiconductor A-9PTE . . . . . . . . . . . . . . . . . . . . Page Table EntryPTI. . . . . . . . . . . . . . . .

MPC5200B Users Guide, Rev. 1A-10 Freescale SemiconductorSScalability . . . . . . . . . . . . . . . The capability of an architecture to generate imple

MPC5200B Users Guide, Rev. 12-30 Freescale SemiconductorPinout TablesTable 2-8. LocalPlus Dedicated SignalsPIN / BALL NUMBER FunctionResetValueDescrip

TMPC5200B Users Guide, Rev. 1Freescale Semiconductor A-11stp . . . . . . . . . . . . . . . . . . . . . stopstr . . . . . . . . . . . . . . . . . . .

MPC5200B Users Guide, Rev. 1A-12 Freescale SemiconductorWVBR . . . . . . . . . . . . . . . . . . . Variable Bit-RateVC. . . . . . . . . . . . . . . .

MPC5200B Users Guide, Rev. 1Freescale Semiconductor B-1Appendix BList of RegistersSection 5.5 CDM Registers ...

MPC5200B Users Guide, Rev. 1B-2 Freescale Semiconductor7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR + 0x0B30 ...

MPC5200B Users Guide, Rev. 1Freescale Semiconductor B-3Section 9.7.2 SCLPC Registers—MBAR + 0x3C00 ...

MPC5200B Users Guide, Rev. 1B-4 Freescale Semiconductor10.3.3.1.6 Tx Last Word PCITLWR(R) —MBAR + 0x3814...

MPC5200B Users Guide, Rev. 1Freescale Semiconductor B-5Section 11.3.3 ATA Drive Registers—MBAR + 0x3A00...

MPC5200B Users Guide, Rev. 1B-6 Freescale Semiconductor13.15.8 SDMA Task Control 0 Register—MBAR + 0x121C ...

MPC5200B Users Guide, Rev. 1Freescale Semiconductor B-7Section 14.8 FEC Tx FIFO Status Register—MBAR + 0x31A8...

MPC5200B Users Guide, Rev. 1B-8 Freescale Semiconductor15.2.43 Tx FIFO Write Pointer (0x96)—TFWPTR ...

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-31Figure 2-4. PSC1 Port Map—5 PinsTable 2-9. PSC1 Pin FunctionsPin Name Dir. GPIO A

MPC5200B Users Guide, Rev. 1Freescale Semiconductor B-919.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D...

MPC5200B Users Guide, Rev. 1B-10 Freescale Semiconductor

How to Reach Us:Home Page:www.freescale.comE-mail:[email protected]/Europe or Locations Not Listed:Freescale SemiconductorTechnical Information

MPC5200B Users Guide, Rev. 12-32 Freescale SemiconductorPinout TablesTable 2-10. PSC1 Functions by PinPIN / BALL NUMBER FunctionResetValueDescriptionP

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-33Pin PSC1_3 Ball B10GPIO hi - z GPIOSimple General Purpose I/OAC97_1 hi

MPC5200B Users Guide, Rev. 12-34 Freescale SemiconductorPinout TablesFigure 2-5. PSC2 Port Map—5 PinsTable 2-11. PSC2 Pin FunctionsPin NameDir. GPIO C

Table of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1Freescale Semiconductor TOC-710.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380C ..

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-35Table 2-12. PSC2 Functions by PinPIN / BALL NUMBER FunctionResetValueDescriptionP

MPC5200B Users Guide, Rev. 12-36 Freescale SemiconductorPinout TablesPin PSC2_3 Ball B08GPIO hi - z GPIOSimple General Purpose I/OCAN1, CAN2

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-37Figure 2-6. PSC3 Port Map—10 PinsTable 2-13. PSC3 Pin FunctionsPin name Dir. GPIO

MPC5200B Users Guide, Rev. 12-38 Freescale SemiconductorPinout TablesTable 2-14. PSC3 Pin Functions (cont.)Pin name Dir. CODEC3 w/ M SPI UART3 / SPI U

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-39Pin PSC3_1 Ball B07GPIO hi - z GPIOSimple General Purpose I/OUSB2 hi -

MPC5200B Users Guide, Rev. 12-40 Freescale SemiconductorPinout TablesPin PSC3_3 Ball C06GPIO hi - z GPIOSimple General Purpose I/OUSB2 hi -

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-41Pin PSC3_5 Ball A06GPIO hi - z LP_CS_7USB2 hi - z USB2_RXNUSB Receive

MPC5200B Users Guide, Rev. 12-42 Freescale SemiconductorPinout TablesPin PSC3_7 Ball B05GPIO hi - z GPIOSimple General Purpose I/OUSB2 hi -

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-43Figure 2-7. USB Port Map—10 PinsPin PSC3_9 Ball C04GPIO hi - z GPIO_W/

MPC5200B Users Guide, Rev. 12-44 Freescale SemiconductorPinout TablesTable 2-16. USB Pin FunctionsPin NameDir.Reset ConfigurationGPIO USB 2x UART4/5US

Table Of ContentsParagraph PageNumber NumberMPC5200B Users Guide, Rev. 1TOC-8 Freescale Semiconductor10.4.6.2 Addressing ...

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-45Pin USB_3 Ball G01GPIO hi - z ----USB1 hi - z USB1_RXDUSB1 Receive Data

MPC5200B Users Guide, Rev. 12-46 Freescale SemiconductorPinout TablesFigure 2-8. Ethernet Output Port Map—8 PinsPin USB_9 Ball F03GPIO hi -

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-47Figure 2-9. Ethernet Input / Control Port Map—10 PinsTable 2-18. Ethernet Pin Fun

MPC5200B Users Guide, Rev. 12-48 Freescale SemiconductorPinout TablesETH_9 I/O GPIO GPIO ETH7_RXCLK ETH7_RXCLKETH_10 I/O GPIO GPIO ETH7_COL ETH7_COLET

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-49ETH_16 I/O ETH18_RXERR ETH18_w/MD_RXERRUART4e__DCD INTERRUPT UART4_CD INTERRUPT I

MPC5200B Users Guide, Rev. 12-50 Freescale SemiconductorPinout TablesPin ETH_1 Ball K02GPIO hi - z GPIOSimple General Purpose OutputUSB2 hi

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-51Pin ETH_2 Ball K03GPIO hi - z GPIOSimple General Purpose OutputUSB2 hi

MPC5200B Users Guide, Rev. 12-52 Freescale SemiconductorPinout TablesPin ETH_3 Ball J01GPIO hi - z GPIOSimple General Purpose OutputUSB2 hi

Pinout TablesMPC5200B Users Guide, Rev. 1Freescale Semiconductor 2-53Pin ETH_4 Ball J02GPIO hi - z GPIOSimple General Purpose OutputUSB2 hi

MPC5200B Users Guide, Rev. 12-54 Freescale SemiconductorPinout TablesPin ETH_5 Ball L03GPIO hi - z GPIOSimple General Purpose OutputUSB2 hi