Freescale Semiconductor DSP56364 Instrukcja Użytkownika Pobierz pdf (Strona 16)

DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2

xvi Freescale Semiconductor

Manual Conventions

The following conventions are used in this manual:

• Bits within registers are always listed from most significant bit (MSB) to least significant bit

(LSB).

• When several related bits are discussed, they are referenced as AA[n:m], where n>m. For purposes

of description, the bits are presented as if they are contiguous within a register. However, this is not

always the case. Refer to the programming model diagrams or to the programmer’s sheets to see

the exact location of bits within a register.

• When a bit is described as “set”, its value is 1. When a bit is described as “cleared”, its value is 0.

• The word “assert” means that a high true (active high) signal is pulled high to V

or that a low

true (active low) signal is pulled low to ground. The word “deassert” means that a high true signal

is pulled low to ground or that a low true signal is pulled high to V

• Pins or signals that are asserted low (made active when pulled to ground)

— In text, have an overbar (e.g., RESET is asserted low).

— In code examples, have a tilde in front of their names. In example below, line 3 refers to the

SS0 pin (shown as ~SS0).

• Sets of pins or signals are indicated by the first and last pins or signals in the set (e.g., HA1–HA8).

• Code examples are displayed in a monospaced font, as shown below:

• Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFFFF is the

X memory address for the core interrupt priority register (IPR-C).

• The word “reset” is used in four different contexts in this manual:

— the reset signal, written as “RESET,”

High True/Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

PIN is a generic term for any pin on the chip.

True Asserted Ground

Ground is an acceptable low voltage level. See the appropriate data sheet for the range of

acceptable low voltage levels (typically a TTL logic low).

PIN False Deasserted V

is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable

high voltage levels (typically a TTL logic high).

PIN True Asserted V

PIN False Deasserted Ground

Example Sample Code Listing

BFSET #$0007,X:PCC; Configure: line 1

; MISO0, MOSI0, SCK0 for SPI master line 2

; ~SS0 as PC3 for GPIO line 3

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 183 184

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