Freescale-semiconductor MPC5200B Instrukcja Użytkownika Strona 702
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Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-23
Figure 20-7. J1850 VPW EOF and IFS Symbols
• Valid EOF & IFS Symbol
In Figure 20-7(1), if the passive to active transition beginning the SOF symbol of the next message occurs between T
rv4(Min)
and
T
rv4(Max)
, the current symbol will be considered a valid EOF symbol.
If the passive to active transition beginning the SOF symbol of the next message occurs after T
rv5(Min)
, the current symbol will be
considered a valid EOF symbol followed by a valid IFS symbol. See Figure 20-7(2). All nodes must wait until a valid IFS symbol
time has expired before beginning transmission. However, due to variations in clock frequencies and bus loading, some nodes may
recognize a valid IFS symbol before others, and immediately begin transmitting. Therefore, anytime a node waiting to transmit
detects a passive to active transition once a valid EOF has been detected, it should immediately begin transmission, initiating the
arbitration process.
• Idle Bus
If the passive to active transition beginning the SOF symbol of the next message does not occur before T
tv5(Min)
, the bus is
considered to be idle, and any node wishing to transmit a message may do so immediately.
(2) Valid EOF+
IFS Symbol
280µs
300µs
T
rv4(Min)
T
rv4(Max)
(1) Valid EOF
Symbol
Active
Passive
Active
Passive
T
rv5(Min)
- MPC5200B Users Guide 1
- Table of Contents 2
- Chapter 10 PCI Controller 7
- Chapter 11 ATA Controller 9
- Paragraph Page 10
- Number Number 10
- Chapter 16 XLB Arbiter 15
- Appendix A Acronyms and Terms 19
- Appendix B List of Registers 19
- List of Figures 20
- Figure Page 21
- LOF-4 Freescale Semiconductor 23
- List of Tables 24
- Table Page 25
- Revision History 34
- Freescale Semiconductor 35
- Chapter 1 36
- Introduction 36
- 1.2 Architecture 37
- 1.2.1 Embedded e300 Core 40
- 1.2.2 BestComm I/O Subsystem 41
- 1.2.5 System Level Interfaces 42
- 1.2.8 Power Management 43
- 1.2.9 Systems Debug and Test 44
- 1-10 Freescale Semiconductor 45
- Architecture 45
- Chapter 2 46
- View Looking at Pins (Balls) 47
- Freescale Semiconductor 2-3 48
- 2.2 Pinout Tables 49
- 2-14 Freescale Semiconductor 59
- Freescale Semiconductor 2-15 60
- 2-16 Freescale Semiconductor 61
- Freescale Semiconductor 2-17 62
- 2-18 Freescale Semiconductor 63
- Freescale Semiconductor 2-19 64
- Pin EXT_AD_19 Ball Y04 65
- Freescale Semiconductor 2-21 66
- 2-22 Freescale Semiconductor 67
- Freescale Semiconductor 2-23 68
- 2-24 Freescale Semiconductor 69
- Freescale Semiconductor 2-25 70
- 2-26 Freescale Semiconductor 71
- Freescale Semiconductor 2-27 72
- 2-28 Freescale Semiconductor 73
- Freescale Semiconductor 2-29 74
- 2-30 Freescale Semiconductor 75
- 2-32 Freescale Semiconductor 77
- Freescale Semiconductor 2-33 78
- Freescale Semiconductor 2-35 80
- 2-36 Freescale Semiconductor 81
- GPIOUSB2UART3(e) CODEC3 SPI 82
- GPIO hi - z LP_CS_6 85
- Function 88
- Port_conf 88
- Table 2-16. USB Pin Functions 89
- ETH_0 ETH_1 ETH_2 ETH_3 ETH_4 91
- ETH_5 ETH_6 ETH_7 91
- Freescale Semiconductor 2-49 94
- 2-50 Freescale Semiconductor 95
- Freescale Semiconductor 2-51 96
- 2-52 Freescale Semiconductor 97
- Freescale Semiconductor 2-53 98
- 2-54 Freescale Semiconductor 99
- Pinout Tables 100
- Freescale Semiconductor 2-55 100
- 2-56 Freescale Semiconductor 101
- Notes: 101
- Freescale Semiconductor 2-57 102
- 2-58 Freescale Semiconductor 103
- Freescale Semiconductor 2-59 104
- 2-60 Freescale Semiconductor 105
- Freescale Semiconductor 2-61 106
- PIN / BALL NUMBER Function 108
- Description 108
- Freescale Semiconductor 2-67 112
- I2C_0 I2C_1 I2C_2 I2C_3 112
- MPC5200B Users Guide, Rev. 1 113
- Signal Descriptions 119
- 2-74 Freescale Semiconductor 119
- Chapter 3 120
- Memory Map 120
- 3.3 MPC5200B Memory Map 122
- 3.3.2.2 LocalPlus Bus 123
- Name Description 124
- Chapter 4 128
- 4.3 Reset Sequence 129
- 4.4 Reset Operation 129
- 4.5 Other Resets 130
- 4.6 Reset Configuration 131
- 4-6 Freescale Semiconductor 133
- Chapter 5 134
- Clocks and Power Management 134
- System APLL 136
- Core APLL 136
- Table 5-2. System PLL Ratios 137
- 5.3.2 e300 Core Clock Domain 138
- DDR SDRAM Memory Clocks 141
- SDR SDRAM Memory Clocks 141
- 5.4 Power Management 142
- 5.4.4 Deep-Sleep Mode 143
- 5.5 CDM Registers 144
- ) Manufacturer (Freescale) 145
- 5-24 Freescale Semiconductor 157
- CDM Registers 157
- Chapter 6 158
- Chapter 7 160
- System Integration Unit (SIU) 160
- 7.2.2 Interface Description 163
- 7.2.3 Programming Note 163
- (IC, OC, PWM) 163
- Reserved 168
- Table 7-20. GPIO Pin List 181
- 7.3.1 GPIO Pin Multiplexing 184
- 7.3.1.4 USB1/RST_CONFIG 185
- 7.3.1.6 PSC6 186
- 7.3.1.7 I 186
- 7.3.1.8 GPIO Timer Pins 186
- 7.3.2 GPIO Programmer’s Model 187
- —MBAR + 0x0B00 188
- —MBAR + 0x0B04 190
- 0x0C00. Register addresses 206
- 7.4.2 Mode Overview 214
- 7.4.3 Programming Notes 214
- to this offset 215
- 7.5 Slice Timers 221
- SLT 1 Terminal Count Register 222
- SLT 1 Control Register 222
- SLT 1 Count Value Register 223
- 7.6 Real-Time Clock 224
- 7.6.1 Real-Time Clock Signals 225
- 7.6.2 Programming Note 225
- 7-74 Freescale Semiconductor 233
- Real-Time Clock 233
- Chapter 8 234
- SDRAM Memory Controller 234
- 8.3 Features 235
- 8.3.1 Devices Supported 236
- 8.4 Functional Description 248
- 8.4.2 Block Diagram 249
- 8.4.3 Transfer Size 249
- 8.4.4 Commands 250
- 8.4.4.4 Read Command 251
- 8.4.4.5 Write Command 251
- 8.5 Operation 252
- 8.5.2 Read Clock 253
- Table 8-7. High Address Usage 256
- 8.8 Address Bus Mapping 263
- 8-32 Freescale Semiconductor 265
- Address Bus Mapping 265
- row address bit, the 265
- Chapter 9 266
- 9.3 Interface 267
- 9.3.2 Block Diagram 268
- 9.4 Modes of Operation 269
- Valid Address 271
- Valid write Data 271
- Valid read Data 271
- 9.4.2 MUXed Mode 272
- 9.4.2.1 Address Tenure 273
- 9.4.2.2 Data Tenure 273
- 9.5 Configuration 274
- 9.5.3 Reset Configuration 275
- 9.7 Programmer’s Model 276
- 9-32 Freescale Semiconductor 297
- Chapter 10 298
- PCI Controller 298
- External 299
- 10.2.6.1 PCI_PAR - Parity 300
- 10.3 Registers 301
- Mnemonic Name 302
- Section 3.2, Internal 303
- Table 1 316
- 7PCI Arbiter Soft 320
- Bits Name Description 325
- 10.4 Functional Description 341
- 10.4.1 PCI Bus Protocol 342
- 10.4.1.3 PCI Transactions 343
- 10.4.1.4 PCI Bus Commands 344
- 10.4.1.5 Addressing 345
- 10.4.2 Initiator Arbitration 348
- 10.4.4.1 Endian Translation 349
- 10.4.5.2 Local Memory Writes 355
- 10.4.5.3 Data Translation 355
- 10.4.5.4 Target Abort 356
- 10.4.5.5 Latrule Disable 356
- 10.4.6.1 Access Width 357
- 10.4.6.2 Addressing 357
- 10.4.6.3 Data Translation 357
- 10.4.6.4 Initialization 357
- 10.4.6.5 Restart and Reset 358
- 10.4.6.6 PCI Commands 358
- 10.4.6.7 FIFO Considerations 358
- 10.5 PCI Arbiter 359
- 10.6 Application Information 360
- 10.6.2 Address Maps 361
- 10-68 Freescale Semiconductor 365
- Application Information 365
- Chapter 11 366
- ATA Controller 366
- 11.3 ATA Register Interface 367
- Table 11-12. ata_shre_cnt 373
- 2. Repeat 383
- 11.4.1 PIO State Machine 386
- 11.4.2 DMA State Machine 387
- 11.5 Signals and Connections 388
- 11.7 ATA Bus Background 391
- 11.7.2 ATA Modes 392
- 11.7.3 ATA Addressing 392
- 11.7.3.2 Drive Interrupt 393
- 11.7.3.3 Sector Addressing 393
- 11.7.4 ATA Transactions 395
- 11.7.4.1.1 Class 1—PIO Read 395
- 11.7.4.1.2 Class 2—PIO Write 396
- shows the Non-Data Command 397
- 11-34 Freescale Semiconductor 399
- ATA Bus Background 399
- 11.7.4.4 Ultra DMA Protocol 400
- 11.8 ATA RESET/Power-Up 401
- 11-38 Freescale Semiconductor 403
- 12.1 Overview 404
- 12.2 Data Transfer Types 404
- 12.3.1 Communication Channels 405
- 12.3.2 Data Structures 406
- 12.4.1 Programming Note 408
- Universal Serial Bus (USB) 433
- 12-30 Freescale Semiconductor 433
- Chapter 13 434
- BestComm 434
- 13.3 Features summary 435
- 13.4 Descriptors 435
- 13.5 Tasks 435
- —MBAR + 0x1210 439
- SDMA Task Control 1 Register 442
- SDMA Task Control 3 Register 443
- SDMA Task Control 5 Register 444
- SDMA Task Control 7 Register 444
- SDMA Task Control 9 Register 445
- SDMA Task Control B Register 445
- SDMA Task Control D Register 446
- SDMA Task Control F Register 446
- 13.15.31 SDMA 458
- —MBAR + 0x1278 458
- 13.16 On-Chip SRAM 461
- 13.17 Programming Model 461
- 13.17.2 Variable Table 463
- Contents Comments 464
- 13-32 Freescale Semiconductor 465
- Programming Model 465
- Chapter 14 466
- Tx FIFO (1KByte) 467
- Rx FIFO (1KByte) 467
- 14.2 Modes of Operation 468
- 14.3 I/O Signal Overview 468
- Table 14-6. Module Memory Map 472
- Table 14-7. CSR Counters 472
- Table 14-8. MIB Counters 474
- Table 14-9. FEC ID Register 476
- R Reserved 478
- RESET:0 00000000 0 0 0 00 0 0 478
- 14.6 FIFO Interface 492
- FEC Tx FIFO Status Register 493
- FEC Tx FIFO Control Register 495
- 14.9 Initialization Sequence 499
- 14.9.5 FEC Frame Reception 502
- Initialization Sequence 504
- Freescale Semiconductor 14-39 504
- 14.9.8 Inter-Packet Gap Time 508
- 14.9.9 Collision Handling 508
- 14.9.11.1 Transmission Errors 509
- 14.9.11.2 Reception Errors 509
- 14-46 Freescale Semiconductor 511
- Chapter 15 512
- Interrupt 513
- Control Logic 513
- 15.1.2 Features 514
- Table 15-2. PSC Memory Map 515
- Table 15-9. Stop-Bit Lengths 519
- 0 = No break received 520
- Freescale Semiconductor 15-15 526
- 15-24 Freescale Semiconductor 535
- MclkDiv [8:0] + 1 536
- 0:1 — Reserved 550
- 15.3 PSC Operation Modes 555
- 15.3.2 PSC in Codec Mode 560
- MclkDiv[8:0]+1 561
- Frame length 566
- Data width 569
- IPB clock frequency 570
- 15.3.3 PSC in AC97 Mode 572
- SDATA_OUT 574
- 15.3.4 PSC in IrDA mode 576
- {CTUR:CTLR} 577
- 15.3.4.2 PSC in MIR Mode 578
- 15.3.4.3 PSC in FIR Mode 581
- 15.4 PSC FIFO System 582
- 15.4.2 TX FIFO 585
- 15.4.3 Looping Modes 585
- 15.4.4 Multidrop Mode 586
- Chapter 16 588
- XLB Arbiter 588
- 16.1.1.2.1 Bus Grant 589
- 16.1.1.2.2 Parking Modes 589
- 16.1.1.4.1 Timer Functions 589
- (RW)—MBAR + 0x1F70 599
- 16-14 Freescale Semiconductor 601
- Chapter 17 602
- 17.2 SPI Signal Description 603
- Table 17-9. SPI Data Register 608
- 17.4 Functional Description 609
- 17.4.3 Slave Mode 610
- 17.4.4 Transmission Formats 610
- SHIFT REGISTER 611
- 17.4.6 Special Features 614
- SPR 1+() 614
- 17.4.7 Error Conditions 615
- 17.4.8 Low Power Mode Options 615
- 17.4.9 SPI Interrupts 616
- 17-16 Freescale Semiconductor 617
- Functional Description 617
- Chapter 18 618
- Inter-Integrated Circuit (I 618
- C Controller 619
- 18.2.2.2 Data Transfer 620
- 18.2.2.3 Acknowledge 620
- 18.2.2.4 Repeated Start 621
- C Interface Registers 622
- Table 18-2. I 623
- C Address Register 623
- Table 18-3. I 623
- C Frequency Divider Register 623
- 18.3.3 I 630
- 18.3.4 I 632
- 18.3.5 I 633
- 18.3.6 I 634
- 18.3.7 I 635
- 18.4 Initialization Sequence 636
- 18.5.3 Special Note on AKF 637
- Freescale Semiconductor 18-21 638
- 18-22 Freescale Semiconductor 639
- 19.1 Overview 640
- 19.2 Features 641
- 19.3 External Signals 641
- 19.4 CAN System 641
- 19.5.1 Module Memory Map 642
- Table 19-2. Module Memory Map 643
- 19.5.2 Register Descriptions 644
- R SJW[1:0] BRP[5:0] 647
- RESET:00000000 647
- 0x920 / 0x9A0 CANIDR0 657
- 0x921 / 0x9A1 CANIDR1 657
- 0x924 / 0x9A4 CANIDR2 657
- 0x925 / 0x9A5 CANIDR3 657
- 0x930 / 0x9B0 CANIDR4 658
- 0x931 / 0x9B1 CANIDR5 658
- 0x934 / 0x9B4 CANIDR6 658
- 0x935 / 0x9B5 CANIDR7 658
- 0x928 / 0x9A8 CANIDMR0 659
- 0x929 / 0x9A9 CANIDMR1 659
- 0x92C / 0x9AC CANIDMR2 659
- 0x92D / 0x9AD CANIDMR3 659
- 0x938 / 0x9B8 CANIDMR4 660
- 0x939 / 0x9B9 CANIDMR5 660
- 0x93C / 0x9BC CANIDMR6 660
- 0x93D / 0x9BD CANIDMR7 660
- = Unused 661
- 19.7 Functional Description 665
- Receiver 666
- Transmitter 666
- 19.7.2.2 Transmit Structures 667
- 19.7.2.3 Receive Structures 667
- 19-30 Freescale Semiconductor 669
- Freescale Semiconductor 19-31 670
- Bit Rate 672
- 19.7.6 Timer Link 673
- 19.7.7 Modes of Operation 673
- 19.7.8 Low Power Options 673
- 19.7.8.1 CPU Run Mode 674
- 19.7.8.2 CPU Sleep Mode 674
- 19.7.8.3 CPU Deep Sleep Mode 674
- 19.7.8.4 MSCAN Sleep Mode 674
- 19.7.9.1 Transmit Interrupt 677
- 19.7.9.2 Receive Interrupt 677
- 19.7.9.3 Wake-Up Interrupt 677
- 19.7.10 Interrupt Acknowledge 678
- 19-40 Freescale Semiconductor 679
- Chapter 20 680
- CPU Interface 683
- Protocol Handler 683
- MUX Interface 683
- 20.5 Signal Description 684
- 20.6 Overview 684
- 20.7 Memory Map and Registers 684
- — Clock Select (Bit 6) 685
- — Interrupt Enable (Bit 1) 685
- BDLC State Vector Register 686
- Table 1-1. Interrupt Summary 686
- — State Machine Reset (Bit 7) 687
- — 4X Mode Enable (Bit 5) 688
- Corresponding Expected 692
- — Rate Select (Bits 7-0) 693
- — BDLC Enable (Bit 4) 694
- — send BREAK signal (Bit 0) 694
- 20.8 Functional Description 695
- 20.8.1.2 J1850 VPW Symbols 696
- Transmitter A 704
- Transmitter B 704
- J1850 Bus 704
- 20.8.1.4 J1850 Bus Errors 705
- 20.8.2 Mux Interface 706
- 20.8.5.4 Receiving Exceptions 713
- 20.9 Resets 729
- Chapter 21 730
- TAP Link Module 731
- Freescale Semiconductor 21-3 732
- 21.3.1 Test Reset (TRST) 733
- 21.3.2 Test Clock (TCK) 733
- 21.3.3 Test Mode Select (TMS) 733
- 21.3.4 Test Data In (TDI) 733
- 21.4 Slave Test Reset (STRST) 734
- 21.5 TAP State Machines 734
- 21.7 TLM Link DR Instructions 736
- 21.8 TLM Test Instructions 737
- 21.9 e300 COP/BDM Interface 738
- 21-10 Freescale Semiconductor 739
- Appendix A 740
- Acronyms and Terms 740
- Appendix B 752
- List of Registers 752
- B-4 Freescale Semiconductor 755
- B-6 Freescale Semiconductor 757
- Freescale Semiconductor B-7 758
- B-8 Freescale Semiconductor 759
- Freescale Semiconductor B-9 760
- B-10 Freescale Semiconductor 761
- How to Reach Us: 762
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