Freescale-semiconductor StarCore SC140 Instrukcja Użytkownika

SC140 DSP CoreReference ManualRevision 4.1, September 2005This document contains information on a new product. Specifications and information herein a

x SC140 DSP Core Reference Manual7.5.6 Status Bit Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-68 SC140 DSP Core Reference ManualMemory InterfaceTable 2-30 shows the representation of the change-of-flow instructions in big and little endian mo

SC140 DSP Core Reference Manual 3-1Chapter 3Control RegistersThis chapter describes the core control registers for the SC140 core. Several bits in the

3-2 SC140 DSP Core Reference ManualCore Control Registers• ILLEGAL• DEBUG, DEBUGEV (if configured in the EOnCE to generate an exception)The following

Core Control RegistersSC140 DSP Core Reference Manual 3-3LF2Bit 29Loop Flag 2 — When set, indicates that hardware loop #3 is enabled. At the start of

3-4 SC140 DSP Core Reference ManualCore Control RegistersOVE Bit 20Overflow Exception Enable Bit — Enables or disables the generation of an exception

Core Control RegistersSC140 DSP Core Reference Manual 3-5SBit 6Scaling Bit — Set when moving a result from a data register (D0–D15) to memory using a

3-6 SC140 DSP Core Reference ManualCore Control RegistersSMBit 2Arithmetic Saturation Mode — Selects automatic saturation on 32 bits for data arithmet

Core Control RegistersSC140 DSP Core Reference Manual 3-73.1.2 Exception and Mode Register (EMR)The purpose of the EMR is to reflect and control exce

3-8 SC140 DSP Core Reference ManualCore Control RegistersTable 3-2 describes the EMR fields.Table 3-2. EMR DescriptionName Description SettingsRBits

Core Control RegistersSC140 DSP Core Reference Manual 3-9ILSTBit 1Illegal Execution Set — Indicates whether an execution set grouping rule has been vi

SC140 DSP Core Reference Manual xiA.1.5 Prefix Word Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7A

3-10 SC140 DSP Core Reference ManualPLL and Clock Registers3.1.2.1 Clearing EMR BitsThe ILIN, ILST, DOVF, and NMID bits can only be set by the hard

SC140 DSP Core Reference Manual 4-1Chapter 4Emulation and Debug (EOnCE)The SC140 core provides board and chip-level testing capability through two on-

4-2 SC140 DSP Core Reference ManualOverview of the Combined JTAG and EOnCE InterfaceIn addition, the EOnCE:• Reduces system intrusion when debugging i

Overview of the Combined JTAG and EOnCE InterfaceSC140 DSP Core Reference Manual 4-3Figure 4-1. JTAG and EOnCE Multi-core InterconnectionTo access t

4-4 SC140 DSP Core Reference ManualOverview of the Combined JTAG and EOnCE InterfaceFigure 4-2 shows the TAP controller state machine, and Table 4-3 s

Overview of the Combined JTAG and EOnCE InterfaceSC140 DSP Core Reference Manual 4-5Figure 4-2. TAP Controller State MachineAt power-up or during no

4-6 SC140 DSP Core Reference ManualOverview of the Combined JTAG and EOnCE InterfaceThe first action that occurs when either block is entered is a Cap

Overview of the Combined JTAG and EOnCE InterfaceSC140 DSP Core Reference Manual 4-7Figure 4-3. Cascading Multiple EOnCE Modules4.2.5 DEBUG_REQUEST

4-8 SC140 DSP Core Reference ManualOverview of the Combined JTAG and EOnCE InterfaceFigure 4-4. Reading and Writing EOnCE Registers Via JTAGThe SC14

Overview of the Combined JTAG and EOnCE InterfaceSC140 DSP Core Reference Manual 4-9Figure 4-5. Accessing EOnCE registers through JTAG(A) EOnCE regi

xii SC140 DSP Core Reference Manual

4-10 SC140 DSP Core Reference ManualMain Capabilities of the EOnCE Module4.3 Main Capabilities of the EOnCE ModuleWhile the JTAG port provides board

Main Capabilities of the EOnCE ModuleSC140 DSP Core Reference Manual 4-114.3.2 EOnCE Dedicated InstructionsThe instruction set of the SC140 core arch

4-12 SC140 DSP Core Reference ManualMain Capabilities of the EOnCE ModuleIf the core is in execution state or in a power-saving state (stop or wait) w

Main Capabilities of the EOnCE ModuleSC140 DSP Core Reference Manual 4-13Figure 4-7. Software Downloading Execute CHOOSE_EOnCE and DEBUG_REQUEST in

4-14 SC140 DSP Core Reference ManualMain Capabilities of the EOnCE Module4.3.7 EOnCE EventsAn emulator event is an occurrence that the emulator can c

Main Capabilities of the EOnCE ModuleSC140 DSP Core Reference Manual 4-154.3.8 EOnCE ActionsAn emulator action is something that the EOnCE does as a

4-16 SC140 DSP Core Reference ManualEOnCE Enabling and Power Considerations4.4 EOnCE Enabling and Power ConsiderationsExcept for the EOnCE controlle

EOnCE Module Internal ArchitectureSC140 DSP Core Reference Manual 4-17• Reading and writing EOnCE registers from the software• Real-time JTAG port acc

4-18 SC140 DSP Core Reference ManualEOnCE Module Internal ArchitectureThe functionality of the EOnCE controller registers is described in Section 4.7,

EOnCE Module Internal ArchitectureSC140 DSP Core Reference Manual 4-19Figure 4-9 shows a block diagram of the event counter. Figure 4-9. Event Count

SC140 DSP Core Reference Manual xiii1-1 Block Diagram of a Typical SoC Configuration with the SC140 Core . . . . . . . 1-52-1 Block Diagram of the SC

4-20 SC140 DSP Core Reference ManualEOnCE Module Internal Architecture4.5.3 Event Detection Unit (EDU)The EOnCE EDU capabilities are:• Event detectio

EOnCE Module Internal ArchitectureSC140 DSP Core Reference Manual 4-21In the case of read-modify-write commands, the EDU generates an event even if th

4-22 SC140 DSP Core Reference ManualEOnCE Module Internal Architecture4.5.3.1 Address Event Detection Channel (EDCA)One of the main elements of the

EOnCE Module Internal ArchitectureSC140 DSP Core Reference Manual 4-23• Greater thanEach EDCA includes four registers, as shown in Table 4-8.The funct

4-24 SC140 DSP Core Reference ManualEOnCE Module Internal Architecture4.5.3.2 Data Event Detection Channel (EDCD)The EDCD is one of the main element

EOnCE Module Internal ArchitectureSC140 DSP Core Reference Manual 4-254.5.3.3 Optional External Event Detection Address ChannelsThe EDU has two port

4-26 SC140 DSP Core Reference ManualEOnCE Module Internal ArchitectureThe ES block diagram is shown in Figure 4-13. Figure 4-13. Event Selector Bloc

EOnCE Module Internal ArchitectureSC140 DSP Core Reference Manual 4-27— Return from exception instructions• Other change of flow events:— Interrupts—

4-28 SC140 DSP Core Reference ManualEOnCE Module Internal ArchitectureFigure 4-14 displays a block diagram of the trace unit.Figure 4-14. Trace Unit

EOnCE Module Internal ArchitectureSC140 DSP Core Reference Manual 4-29— BREAK— CONT, CONTD— SKIPLSNote that TRAP, and ILLEGAL are traced as interrupt

xiv SC140 DSP Core Reference Manual4-7 Software Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4-30 SC140 DSP Core Reference ManualEOnCE Register AddressingTable 4-11. Trace Buffer Register SetThe functionality of the trace unit registers is d

EOnCE Register AddressingSC140 DSP Core Reference Manual 4-31Table 4-12 displays the EOnCE register addressing offsets.Table 4-12. EOnCE Register Ad

4-32 SC140 DSP Core Reference ManualEOnCE Register Addressing1C R/W 32 32 EDCA4_REFA EDCA4 reference value A1D R/W 32 32 EDCA5_REFA EDCA5 reference va

EOnCE Register AddressingSC140 DSP Core Reference Manual 4-334.6.1 Reading or Writing EOnCE Registers Using Core SoftwareThe core can read or write m

4-34 SC140 DSP Core Reference ManualEOnCE Register AddressingThe ACK bit could be checked on TDO by executing a “neutral” JTAG EOnCE command such as “

EOnCE Register AddressingSC140 DSP Core Reference Manual 4-35Accessibility of the registers through JTAG is the same as from software with the followi

4-36 SC140 DSP Core Reference ManualEOnCE Controller Registers4.7 EOnCE Controller RegistersA list of the EOnCE controller registers is given in Tab

EOnCE Controller RegistersSC140 DSP Core Reference Manual 4-374.7.2 EOnCE Status Register (ESR)The ESR is a 32-bit register. The status bits of the r

4-38 SC140 DSP Core Reference ManualEOnCE Controller RegistersThe shaded bits are reserved and should be initialized with zeros for future software co

EOnCE Controller RegistersSC140 DSP Core Reference Manual 4-39TBFULLBit 25Trace Buffer Full — Indicates that the trace buffer of EOnCE is full. In ord

SC140 DSP Core Reference Manual xv2-1 DALU Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72-2 Wr

4-40 SC140 DSP Core Reference ManualEOnCE Controller RegistersDREE3Bit 13Debug Reason is EE3 — Set when the core enters debug state or executes a debu

EOnCE Controller RegistersSC140 DSP Core Reference Manual 4-414.7.3 EOnCE Monitor and Control Register (EMCR)The EMCR is a 32-bit register. Bits 31–1

4-42 SC140 DSP Core Reference ManualEOnCE Controller RegistersDEBUGERSTBits 21–18Debugger Status Information — If several applications (debugger proce

EOnCE Controller RegistersSC140 DSP Core Reference Manual 4-434.7.4 EOnCE Receive Register (ERCV)ERCV is a 64-bit shift register that can be written

4-44 SC140 DSP Core Reference ManualEOnCE Controller Registers4.7.6 EE SignalsEE signals are general-purpose core interfaces which serve as input or

EOnCE Controller RegistersSC140 DSP Core Reference Manual 4-454.7.6.1.4 Status Bit of the ETRSMT RegisterThe EE4 signal can be programmed to serve a

4-46 SC140 DSP Core Reference ManualEOnCE Controller RegistersThe functionality of EE signals when programmed as an input depends on the programming o

EOnCE Controller RegistersSC140 DSP Core Reference Manual 4-47EE2DEFBits 5–4EE2 Definition — Programs the EE2 signal. Programmed as an output of the E

4-48 SC140 DSP Core Reference ManualEOnCE Controller Registers4.7.7 Core Command Register (CORE_CMD)The CORE_CMD register is used to execute instruct

EOnCE Controller RegistersSC140 DSP Core Reference Manual 4-494.7.8 PC of the Exception Execution Set (PC_EXCP)PC_EXCP enables the user to determine

xvi SC140 DSP Core Reference Manual4-2 JTAG Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-50 SC140 DSP Core Reference ManualEvent Counter Registers• This event was programmed in ESEL_DM.• The debug reason bits (DREDCA0-5, DREDCD) in ESR i

Event Counter RegistersSC140 DSP Core Reference Manual 4-51ascertain the number of cycles needed by a device to get from a starting address to an endi

4-52 SC140 DSP Core Reference ManualEvent Counter Registers4.8.2 Event Counter Value Register (ECNT_VAL)This 32-bit register is used to determine how

Event Counter RegistersSC140 DSP Core Reference Manual 4-534.8.3 Extension Counter Value Register (ECNT_EXT)This is a 32-bit register that is used in

4-54 SC140 DSP Core Reference ManualEvent Detection Unit (EDU) Channels and Registers4.9 Event Detection Unit (EDU) Channels and RegistersThe variou

Event Detection Unit (EDU) Channels and RegistersSC140 DSP Core Reference Manual 4-55EDCAENBits 13–10Event Detection Channel (EDCAi) Enable — Used to

4-56 SC140 DSP Core Reference ManualEvent Detection Unit (EDU) Channels and RegistersIn order to detect a watchpoint on a PC range, one EDCA is enough

Event Detection Unit (EDU) Channels and RegistersSC140 DSP Core Reference Manual 4-57the range on bus B, and the two EDCA events should be OR-ed in th

4-58 SC140 DSP Core Reference ManualEvent Detection Unit (EDU) Channels and Registers4.9.2 Data Event Detection Channel (EDCD)In order to set a watch

Event Detection Unit (EDU) Channels and RegistersSC140 DSP Core Reference Manual 4-59AWSBits 9–8Access Width Selection — Determines the width of the d

SC140 DSP Core Reference Manual xvii5-18 Exit Wait Processing State due to an Interrupt or NMI . . . . . . . . . . . . . . . . . . 5-455-19 Exception

4-60 SC140 DSP Core Reference ManualEvent Detection Unit (EDU) Channels and RegistersEDCDENBits 6–3EDCD Enable — Used to enable or disable the EDCD. W

Event Selector (ES) RegistersSC140 DSP Core Reference Manual 4-614.9.2.2 EDCD Reference Value Register (EDCD_REF)EDCD_REF is a 32-bit register used

4-62 SC140 DSP Core Reference ManualEvent Selector (ES) RegistersFigure 4-23 displays the bit configuration of ESEL_CTRL.The shaded bits are reserved

Event Selector (ES) RegistersSC140 DSP Core Reference Manual 4-63For each outcome, the individual events could be AND-ed or OR-ed as specified in ESEL

4-64 SC140 DSP Core Reference ManualEvent Selector (ES) Registers4.10.3 Event Selector Mask Debug ExceptionRegister (ESEL_DI)This 16-bit register has

Trace Unit RegistersSC140 DSP Core Reference Manual 4-654.10.5 Event Selector Mask Disable Trace Register (ESEL_DTB)This 16-bit register has one bit

4-66 SC140 DSP Core Reference ManualTrace Unit RegistersIn addition, the counter values could be added to the trace package of each trace event, there

Trace Unit RegistersSC140 DSP Core Reference Manual 4-67In order to ensure that the LSB value of the trace data is always valid according to this conv

4-68 SC140 DSP Core Reference ManualTrace Unit RegistersTLOOPBit 5Trace Loops Mode — Enables tracing the addresses of hardware loops. When the bit is

Trace Unit RegistersSC140 DSP Core Reference Manual 4-694.11.2 Trace Buffer Read Pointer Register (TB_RD)TB_RD is a 16-bit register that points to th

xviii SC140 DSP Core Reference Manual

4-70 SC140 DSP Core Reference ManualTrace Unit Registers

SC140 DSP Core Reference Manual 5-1Chapter 5Program ControlThis chapter describes the program control features for the SC140 including:• Pipeline• Ins

5-2 SC140 DSP Core Reference ManualPipelineTo support parallel execution, the core uses a variable length execution set (VLES) architecture with a sta

PipelineSC140 DSP Core Reference Manual 5-3Table 5-1 shows a typical pipeline flow. For the machine to advance to the next instruction cycle, all of t

5-4 SC140 DSP Core Reference ManualPipeline5.1.1.1 Instruction Pre-Fetch and FetchThe first two stages of the pipeline are the pre-fetch and fetch s

Instruction GroupingSC140 DSP Core Reference Manual 5-55.1.1.4 ExecutionDuring the execution stage, all DALU arithmetic calculations are performed b

5-6 SC140 DSP Core Reference ManualInstruction GroupingIn the execution set described above, six SC140 instructions are grouped together. When execute

Instruction GroupingSC140 DSP Core Reference Manual 5-7Prefix grouping can group together any instructions that have available execution units. Howeve

5-8 SC140 DSP Core Reference ManualInstruction Grouping5.2.2 Prefix TypesThe SC140 architecture supports 2 types of prefix instructions, each is used

Instruction GroupingSC140 DSP Core Reference Manual 5-95.2.2.2 One-Word Low Register PrefixThe One-Word Low register prefix encodes all information

SC140 DSP Core Reference Manual xix3-1 Clearing an EMR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5-10 SC140 DSP Core Reference ManualInstruction Grouping5.2.4 Prefix Selection AlgorithmThe grouping method (or encoding of prefix words) is not spec

Instruction GroupingSC140 DSP Core Reference Manual 5-11Figure 5-3. Low Register Prefix Selection AlgorithmYesUse a two-word prefix.NoContinueIs the

5-12 SC140 DSP Core Reference ManualInstruction Grouping5.2.5 Instruction Reordering Within an Execution SetThe SC140 can execute up to four DALU ins

Instruction GroupingSC140 DSP Core Reference Manual 5-13Example 5-3. Execution Set with Three One-word and Two Two-word InstructionsPosition 0 1 2 3

5-14 SC140 DSP Core Reference ManualInstruction TimingGiven the execution set in Example 5-5, the assembler adds a NOP to the object code for correct

Instruction TimingSC140 DSP Core Reference Manual 5-15Table 5-5 summarizes the timing of the various categories of SC140 instructions.Table 5-5. Ins

5-16 SC140 DSP Core Reference ManualInstruction Timing5.3.1.1 DALU Instruction TimingDALU instructions are the most timing-critical instructions in

Instruction TimingSC140 DSP Core Reference Manual 5-175.3.2 Change-Of-Flow Instruction TimingThe change-of-flow (COF) instructions include branches,

5-18 SC140 DSP Core Reference ManualInstruction TimingTable 5-7. Loop Change-Of-Flow Instructions5.3.2.1 Direct, PC-Relative, and Conditional COFT

Instruction TimingSC140 DSP Core Reference Manual 5-195.3.2.2 Delayed COFWhen a change-of-flow instruction is executed, the core must wait for the p

SC140 DSP Core Reference ManualLICENSOR is defined as Freescale Semiconductor, Inc. LICENSOR reserves the right to makechanges without further notice

xx SC140 DSP Core Reference Manual7-7 Duplicate Stack Pointer Destinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-97-8 D

5-20 SC140 DSP Core Reference ManualInstruction Timingchange-of-flow occurs to a new execution set spread over two fetch sets, two new fetches must be

Instruction TimingSC140 DSP Core Reference Manual 5-215.3.3 Memory Access TimingThe SC140 core executes up to one execution set per cycle. The progra

5-22 SC140 DSP Core Reference ManualInstruction TimingThe read or write for each memory access can be mapped to the execution cycle in which they oper

Instruction TimingSC140 DSP Core Reference Manual 5-23cycle-by-cycle basis. Accesses issued on the same cycle may cause a contention. The cases where

5-24 SC140 DSP Core Reference ManualInstruction TimingExample 5-11 shows the parallel execution of a bit mask and a pop instruction. The example disti

Hardware LoopsSC140 DSP Core Reference Manual 5-255.4 Hardware LoopsOne of the most important features of a DSP algorithm is efficient loop executio

5-26 SC140 DSP Core Reference ManualHardware Loops5.4.1.2 Loop Counter Registers (LCn)The LCn registers are 32-bit read/write registers used to defi

Hardware LoopsSC140 DSP Core Reference Manual 5-27Table 5-9 illustrates the location of these marker bits and their functionality in both short and lo

5-28 SC140 DSP Core Reference ManualHardware Loops5.4.4 Loop NestingThe core has four hardware loops (LOOP0, LOOP1, LOOP2 and LOOP3) to execute up to

Hardware LoopsSC140 DSP Core Reference Manual 5-295.4.6 Loop Control InstructionsTable 5-10 lists the loop instructions.The instructions that activat

SC140 DSP Core Reference Manual xxi7-44 SR Write to SR Status Bit Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-267-4

5-30 SC140 DSP Core Reference ManualHardware Loopsinstruction to the last address, the LPMARKA bit will be placed at LA in addition to the LPMARKB bit

Hardware LoopsSC140 DSP Core Reference Manual 5-31The following is an example of a short loop in one execution set.Example 5-15. Short Loop, One Exe

5-32 SC140 DSP Core Reference ManualStack Support5.4.7 Loop TimingIf the loop starting address is not aligned (meaning that the first execution set i

Stack SupportSC140 DSP Core Reference Manual 5-33Memory space is required for interrupts because any task may be active when an interrupt occurs. The

5-34 SC140 DSP Core Reference ManualStack Support5.5.3 Stack Support InstructionsThe core provides push and pop instructions that reference the activ

Stack SupportSC140 DSP Core Reference Manual 5-35Table 5-13 describes the stack memory map while performing a single or a dual push access. Up to two

5-36 SC140 DSP Core Reference ManualStack Support5.5.5 Fast Return from SubroutinesThe SC140 supports a mechanism for speeding up the execution of th

Working ModesSC140 DSP Core Reference Manual 5-375.6 Working ModesThe working mode is determined by the EXP bit in theStatus Register (SR), as shown

5-38 SC140 DSP Core Reference ManualWorking Modes5.6.3 Typical Working Mode Usage ScenariosThe core changes its working modein different ways, depend

Working ModesSC140 DSP Core Reference Manual 5-395.6.3.2 Single-stack RTOSFigure 5-9 illustrates state transitions for a single-stack-based operati

xxii SC140 DSP Core Reference Manual7-81 Illegal use of RAS value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-40 SC140 DSP Core Reference ManualWorking Modes• The EXP bit in the SR is set(if not already), thereby enabling the Exception Stack Pointer (ESP) as

Processing StatesSC140 DSP Core Reference Manual 5-415.7 Processing StatesThe SC140 core is always in one of the five processing states:• Execution•

5-42 SC140 DSP Core Reference ManualProcessing States5.7.2 Processing State TransitionsThe transitions between the states are summarized in the follo

Processing StatesSC140 DSP Core Reference Manual 5-43Table 5-17. Processing State Transitions 5.7.3 Execution StateThe execution state is where ins

5-44 SC140 DSP Core Reference ManualProcessing States5.7.5 Debug StateThe debug state is a special core processing state in which the pipeline is sta

Processing StatesSC140 DSP Core Reference Manual 5-45Table 5-18. Exit Wait Processing State due to an Interrupt or NMI5.7.7 Stop Processing StateTh

5-46 SC140 DSP Core Reference ManualException Processing5.8 Exception ProcessingExceptions are events that interfere with the normal operation of th

Exception ProcessingSC140 DSP Core Reference Manual 5-47Figure 5-11 below depicts the core interface to an external interrupt controller.Figure 5-11.

5-48 SC140 DSP Core Reference ManualException Processing3. The PSEQ services an exception request when ready, typically in five cycles. It may postpon

Exception ProcessingSC140 DSP Core Reference Manual 5-495.8.2 Return From Exception InstructionsReturn from exception should be done with dedicated R

SC140 DSP Core Reference Manual xxiiiAbout This BookThis manual provides reference information for the StarCore SC140 digital signal processor (DSP) c

5-50 SC140 DSP Core Reference ManualException Processing5.8.3 Maskable Interrupts5.8.3.1 Interrupt Priority Level An external maskable interrupt is

Exception ProcessingSC140 DSP Core Reference Manual 5-51If two or more exceptions are pending on the same clock cycle, the one with the higher priorit

5-52 SC140 DSP Core Reference ManualException Processinginstruction also occurred during this period, the ILIN bit in EMR will be set to indicate mult

Exception ProcessingSC140 DSP Core Reference Manual 5-535.8.6.2 Exception Mode ExecutionAn exception mode execution is performed in exactly the same

5-54 SC140 DSP Core Reference ManualException ProcessingThen — The execution set from the target of the exception vector is executed after ES1, and th

Exception ProcessingSC140 DSP Core Reference Manual 5-55Figure 5-12 provides a flow chart for Example 5-17.Figure 5-12. Flowchart for Exception Timi

5-56 SC140 DSP Core Reference ManualException ProcessingThe following pipeline table shows the first case in Example 5-17. ES0 is a JMP with a minimum

SC140 DSP Core Reference Manual 6-57Chapter 6Instruction Set Accelerator Plug-InThis chapter describes the ISAP capability of the SC140 core, and how

6-58 SC140 DSP Core Reference ManualISAP - SC140 Schematic Connection6.2 ISAP - SC140 Schematic ConnectionThe ISAP-SC140 connection actually involve

ISAP - SC140 Schematic ConnectionSC140 DSP Core Reference Manual 6-596.2.2 Multiple ISAPConnection between the core and multiple ISAPs is illustrated

xxiv SC140 DSP Core Reference ManualAbbreviationsThe abbreviations used in this manual are listed below:Table 1. AbbreviationsAbbreviation Descript

6-60 SC140 DSP Core Reference ManualISAP instructions and instruction encoding6.3 ISAP instructions and instruction encodingThis section presents an

ISAP-core register transfersSC140 DSP Core Reference Manual 6-61However, this feature requires some assembler support (core and ISAP) when using such

6-62 SC140 DSP Core Reference ManualImmediate Data Transfer to ISAP registersExample 6-2. ISAP-Core register transfersThe following line of code,cor

Core Assembly Syntax with an ISAPSC140 DSP Core Reference Manual 6-636.7 Core Assembly Syntax with an ISAPThis section describes aspects of the core

6-64 SC140 DSP Core Reference ManualCore Assembly Syntax with an ISAP3rd - abs d0 = a core instructionThe syntax defines that the string between the b

Core Assembly Syntax with an ISAPSC140 DSP Core Reference Manual 6-65Example 6-5. Multiple ISAP coding Two VLES lines that use an explicit ISAP ID s

6-66 SC140 DSP Core Reference ManualCore Assembly Syntax with an ISAPThis is similar example to that shown in Section 6.7.1, “Identification of ISAP i

Programming RulesSC140 DSP Core Reference Manual 6-67line 1: The ift (if true) prefix instruction indicates that the core MAC instructions will be exe

6-68 SC140 DSP Core Reference ManualProgramming Rules6.8.2 Grouping rules for explicit ISAP instructionsG.G.2: up to 8 instruction words per VLESG.G.

Programming RulesSC140 DSP Core Reference Manual 6-696.8.4 Sequencing rules for T bit updateThe ISAP has the ability to change the T bit as a destina

SC140 DSP Core Reference Manual xxvISR Interrupt service routineJTAG Joint test action groupLA Last address LCn Loop counter register nLn Limit tag bi

6-70 SC140 DSP Core Reference ManualProgramming Rules

SC140 DSP Core Reference Manual 7-1Chapter 7Programming RulesThe SC140 has programming rules for correct construction and execution of assembly langua

7-2 SC140 DSP Core Reference ManualVLES Grouping Semantics• All instructions in a VLES execute in parallel. This means:— The assembly source order of

Programming Rule NotationSC140 DSP Core Reference Manual 7-37.3 SC140 Pipeline ExposureThe SC140 has no hardware interlocks, so the pipeline is full

7-4 SC140 DSP Core Reference ManualProgramming Rule Notation7.4.2 Sequencing RulesSequencing rules enforce the VLES sequencing semantics by specifyin

Programming Rule NotationSC140 DSP Core Reference Manual 7-57.4.3.2 B Register AliasingThe B0-7 base registers are the same registers as the R8-15 a

7-6 SC140 DSP Core Reference ManualProgramming Rule Notation7.4.7 AGU Arithmetic Instructions“AGU arithmetic instructions” are those instructions tha

Static Programming RulesSC140 DSP Core Reference Manual 7-77.4.10 Hardware LoopsThe loop count “LCn” and start address “SAn” registers are described

7-8 SC140 DSP Core Reference ManualStatic Programming Rules• The SAn register contains the starting address of the first VLES of long loop n.These ass

Static Programming RulesSC140 DSP Core Reference Manual 7-9Rule G.G.4Instructions grouped in a VLES cannot write to the same register or affect the sa

xxvi SC140 DSP Core Reference ManualRevision HistoryRAS Return address registerRTOS Real-time operating systemSAn Start address register nSF Signed fr

7-10 SC140 DSP Core Reference ManualStatic Programming RulesExample 7-8 Duplicate Register Destinationsmove.w #$1234,d0.h move.w #$5678,d0.l ;not a

Static Programming RulesSC140 DSP Core Reference Manual 7-11Example 7-12 Mutually Exclusive Register Destination Exceptionift add #1,d0 iff add #2,

7-12 SC140 DSP Core Reference ManualStatic Programming RulesRule G.P.1Up to two extension words can be grouped in a VLES. This means:• A three-word in

Static Programming RulesSC140 DSP Core Reference Manual 7-13Rule G.P.3The following instructions in each line are mutually exclusive, and cannot be gr

7-14 SC140 DSP Core Reference ManualStatic Programming RulesExample 7-20. Data Source Use of Nn and Mn Registersmove.l n0,d0 move.l n0,d1 ;not allow

Static Programming RulesSC140 DSP Core Reference Manual 7-15Rule G.P.8 It is not allowed to group AGU instructions that use or update a data register

7-16 SC140 DSP Core Reference ManualStatic Programming Rules7.5.4 AGU RulesRule A.1At least two cycles are required between when an instruction write

Static Programming RulesSC140 DSP Core Reference Manual 7-17Rule A.2At least one cycle is required between a MOVE-like instruction writing to an addre

7-18 SC140 DSP Core Reference ManualStatic Programming RulesIf the VLES having a JT/JF or TRAP instruction is at the end of a program section, the fol

Static Programming RulesSC140 DSP Core Reference Manual 7-19Rule A.7A RTSTK or RTSTKD instruction cannot be grouped in a VLES with a MOVE-like instruc

SC140 DSP Core Reference Manual 1-1Chapter 1IntroductionThe StarCore SC140 digital signal processing (DSP) core, a new member of the SC100 architectur

7-20 SC140 DSP Core Reference ManualStatic Programming RulesRule D.2Core or ISAP instructions that read or write the SR register, affect status bits i

Static Programming RulesSC140 DSP Core Reference Manual 7-21Rule D.4Instructions that read the PC register (implicitly or explicitly) as a source oper

7-22 SC140 DSP Core Reference ManualStatic Programming RulesRule D.8A MOVE-like instruction that reads the SR register is not allowed in the delay slo

Static Programming RulesSC140 DSP Core Reference Manual 7-23Rule T.2.a At least one VLES is required between an ISAP instruction that affects the T st

7-24 SC140 DSP Core Reference ManualStatic Programming RulesThis rule applies to instructions that use the stack pointer (implicitly or explicitly), s

Static Programming RulesSC140 DSP Core Reference Manual 7-25Example 7-43. SR Write to SR Status Bit Usebmclr #$ffff,sr.h ;change SRmove.w #$1234,d0

7-26 SC140 DSP Core Reference ManualStatic Programming RulesRule SR.3At least one VLES is required between a MOVE-like instruction that writes the SR

Static Programming RulesSC140 DSP Core Reference Manual 7-27Example 7-45. DOVF Update to SR Read or Writebmset #$4,emr.lmove.l emr,d2 ;allowedmove.l

7-28 SC140 DSP Core Reference ManualStatic Programming RulesRule SR.7The following instructions that affect status bits in SR cannot be grouped in a V

Static Programming RulesSC140 DSP Core Reference Manual 7-29Rule L.N.2A loop body n must be surrounded by the LOOPSTARTn and LOOPENDn assembly directi

1-2 SC140 DSP Core Reference ManualArchitectural Differentiation1.2 Architectural DifferentiationThe SC140architecture differentiates itself in the

7-30 SC140 DSP Core Reference ManualStatic Programming RulesExample 7-51. DOENn instruction following DOENSHn Instructiondoensh0 #3doen0 #3 dosetup0

Static Programming RulesSC140 DSP Core Reference Manual 7-317.5.8 Loop LA RulesRule L.L.1The following instructions are not allowed at LA-1 or LA of

7-32 SC140 DSP Core Reference ManualStatic Programming RulesRule L.L.3The following instructions are not allowed in a short loop:• COF instructions• S

Static Programming RulesSC140 DSP Core Reference Manual 7-33Rule L.L.5A MOVE-like instruction that writes the SR register is not allowed at LA-4, LA-3

7-34 SC140 DSP Core Reference ManualStatic Programming RulesRule L.D.3The minimum number of VLES between the following instructions that write a LCn r

Static Programming RulesSC140 DSP Core Reference Manual 7-35Example 7-62. SAn Write at the End of Long Loop nloopstart0...doen1 #5...loopstart1...do

7-36 SC140 DSP Core Reference ManualStatic Programming Rules7.5.10 Loop COF RulesRule L.C.1A COF instruction cannot have a COF destination that is LA

Static Programming RulesSC140 DSP Core Reference Manual 7-37Rule L.C.5A Bc or Jc instruction is not allowed at LA-3 of a long loop.Example 7-68. Bc/

7-38 SC140 DSP Core Reference ManualStatic Programming RulesRule L.C.7A loop COF instruction (BREAK, CONT, CONTD, or SKIPLS) in an enabled loop n cann

Static Programming RulesSC140 DSP Core Reference Manual 7-39Rule L.C.9A loop COF instruction (BREAK, CONT, CONTD, or SKIPLS) cannot have a COF destina

Core Architecture FeaturesSC140 DSP Core Reference Manual 1-31.3 Core Architecture FeaturesThe SC140 core consists of the following:• Data arithmeti

7-40 SC140 DSP Core Reference ManualStatic Programming RulesRule L.C.11A delayed COF instruction is not allowed at LA-3 of a long loop.Example 7-72.

Dynamic Programming RulesSC140 DSP Core Reference Manual 7-41Rule L.G.5A loop having one or two VLES must be enabled by a DOENSHn instruction. A loop

7-42 SC140 DSP Core Reference ManualDynamic Programming Rules7.6.2 Memory Access RulesRule A.5Only one memory write instruction to the same location

Dynamic Programming RulesSC140 DSP Core Reference Manual 7-437.6.3 RAS RulesRule J.4Upon execution of the RTS or RTSD instruction, if the RAS is vali

7-44 SC140 DSP Core Reference ManualDynamic Programming Rules7.6.5 Rule Detection Across COF BoundariesSome sequencing rules may be violated across C

Dynamic Programming RulesSC140 DSP Core Reference Manual 7-457.6.5.2 VLES-Based COF RulesVLES-based COF rules are detected like static rules, except

7-46 SC140 DSP Core Reference ManualDynamic Programming Rules7.6.6 Rule Detection Across Exception BoundariesThe SC140 can take an exception at most

Dynamic Programming RulesSC140 DSP Core Reference Manual 7-47Rule A.1aAGU instructions that read the R0-R7 registers with an address register update o

7-48 SC140 DSP Core Reference ManualProgramming Guidelines7.7 Programming GuidelinesThe rules in this section cannot be detected within the visibili

Programming GuidelinesSC140 DSP Core Reference Manual 7-49Rule J.5A program section that ends near a border of reserved memory must end with a non-con

SC140 DSP Core Reference Manual iiiAbout This BookAudience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4 SC140 DSP Core Reference ManualCore Architecture Features1.3.1 Typical System-On-Chip ConfigurationThe SC140 is a high-performance general-purpos

7-50 SC140 DSP Core Reference ManualProgramming Guidelines• Observe the immediate operand ranges as specified within the braces { } in Appendix A.2, “

LPMARK RulesSC140 DSP Core Reference Manual 7-51• Do not write explicit binary encodings using DC (declare constant) assembler directives. It cannot b

7-52 SC140 DSP Core Reference ManualLPMARK Rules7.8.2 Static Programming RulesThis section defines new SC140 LPMARK programming rules for correct LP

LPMARK RulesSC140 DSP Core Reference Manual 7-537.8.3.1.2 Active SAn Register“Active SAn register” is defined as the SAn register where n = the acti

7-54 SC140 DSP Core Reference ManualLPMARK RulesLPMARK Rule L.L.2A DOENn or MOVE-like instruction that writes the active LCn register is not allowed a

LPMARK RulesSC140 DSP Core Reference Manual 7-55LPMARK Rule L.L.6A MOVE-like instruction that writes the SR register is not allowed at LPA-2, LPA-1, L

7-56 SC140 DSP Core Reference ManualLPMARK RulesExample 7-97. Active LCn Read at the Start of a Loopdoensh0 #$10push lc0 ;not allowedinc d0 {lpma

LPMARK RulesSC140 DSP Core Reference Manual 7-57Example 7-98. COF Instructions at LPB of a Long Loop dosetup1 label1 doen1 #n2 move.l #mem_l1,r1 mo

7-58 SC140 DSP Core Reference ManualLPMARK RulesLPMARK Rule L.C.9A loop COF instruction (BREAK, CONT, CONTD, or SKIPLS) cannot have a COF destination

LPMARK RulesSC140 DSP Core Reference Manual 7-59LPMARK Rule L.C.11 + L.C.12A delayed COF instruction is not allowed at LPA-1 or LPB-1 of a loop.Exampl

Core Architecture FeaturesSC140 DSP Core Reference Manual 1-5Figure 1-1. Block Diagram of a Typical SoC Configuration with the SC140 Core1.3.2 Vari

7-60 SC140 DSP Core Reference ManualNOP DefinitionLPMARK Rule L.C.1A COF instruction cannot have a COF destination that is LPB+1 or LPB+2 of a long lo

NOP DefinitionSC140 DSP Core Reference Manual 7-615. Source syntax order in a VLES generally has no effect on the baseline size, as parallel semantics

7-62 SC140 DSP Core Reference ManualNOP Definition[INC D0NOP NOP]is encoded as:[1W prefix, INC, NOP]and[NOPNOP INC D0]is encoded as:[1W prefix, INC, N

NOP DefinitionSC140 DSP Core Reference Manual 7-63[2W IFT-IFF prefix, INC, CLR, NOP]and[IFF CLR D8IFT INC D1 IFT NOP]is encoded (ignoring the NOP subg

7-64 SC140 DSP Core Reference ManualNOP Definition

SC140 DSP Core Reference Manual A-1Appendix ASC140 DSP Core Instruction SetA.1 IntroductionThis appendix describes in detail the SC140 instruction s

A-2 SC140 DSP Core Reference ManualDSP Core Instruction SetA.1.1 ConventionsTable A-1 lists the conventions used in this appendix to define the instr

DSP Core Instruction SetSC140 DSP Core Reference Manual A-3Table A-2 describes the operators and operations syntax for each instruction.Table A-3 desc

A-4 SC140 DSP Core Reference ManualDSP Core Instruction SetTable A-4 lists special syntax used in this appendix to define an instruction’s assembler s

DSP Core Instruction SetSC140 DSP Core Reference Manual A-5A.1.2 Addressing Mode NotationTable A-5 and Table A-6 define the fields in the address off

1-6 SC140 DSP Core Reference ManualCore Architecture Features

A-6 SC140 DSP Core Reference ManualDSP Core Instruction SetA.1.3 Data Representation in Memory for the ExamplesFor the examples in this appendix, the

DSP Core Instruction SetSC140 DSP Core Reference Manual A-7A.1.5 Prefix Word EncodingEach execution set can be associated with a one-word (low or hig

A-8 SC140 DSP Core Reference ManualDSP Core Instruction SetA.1.5.1 One-Word Low Register PrefixIncludes information on grouping, looping, and IFc (c

DSP Core Instruction SetSC140 DSP Core Reference Manual A-9Example:skipl _last ;(there is a skipl to _last in the program)...execution_setexec

A-10 SC140 DSP Core Reference ManualDSP Core Instruction Set Example:lpmarkB;(set LA – 2);(set LA – 1)_last ;(set LA)In the case of a loop with two ex

DSP Core Instruction SetSC140 DSP Core Reference Manual A-11Hh: High register expansion encoding for AGU execution unit 0. This includes all AGU and B

A-12 SC140 DSP Core Reference ManualDSP Core Instruction SetA.1.6 Instruction TypesThe SC140 instruction set is organized into the following instruct

DSP Core Instruction SetSC140 DSP Core Reference Manual A-13Table A-7. DALU Arithmetic Instructions (MAC)Instruction DescriptionABS Absolute valueAD

A-14 SC140 DSP Core Reference ManualDSP Core Instruction SetMPYR Multiply signed fractions and roundMPYSU Multiply signed fraction and unsigned fracti

DSP Core Instruction SetSC140 DSP Core Reference Manual A-15ROL Rotate one bit left through the carry bitROR Rotate one bit right through the carry bi

SC140 DSP Core Reference Manual 2-1Chapter 2Core ArchitectureThis chapter provides an overview of the SC140 core architecture. It describes the main f

A-16 SC140 DSP Core Reference ManualDSP Core Instruction SetTable A-10. AGU Move InstructionsInstruction DescriptionMOVE.2F Move two fractional word

DSP Core Instruction SetSC140 DSP Core Reference Manual A-17Table A-12. AGU Bit-Mask Instructions (BMU)Instruction DescriptionAND Logical AND on a 1

A-18 SC140 DSP Core Reference ManualDSP Core Instruction SetRTED Return from exception (delayed)RTS Return from subroutineRTSD Return from subroutine

DSP Core Instruction SetSC140 DSP Core Reference Manual A-19A.2 InstructionsThe following pages list all of the SC140 instructions and provide speci

A-20 SC140 DSP Core Reference ManualABSAABS Absolute Value (DALU) ABSDescriptionStatus and Conditions that Affect InstructionStatus and Conditions Cha

ABSSC140 DSP Core Reference Manual A-21Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDn FFF Single Sour

A-22 SC140 DSP Core Reference ManualADCADC Add Long With Carry (DALU) ADCDescriptionStatus and Conditions that Affect InstructionStatus and Conditions

ADCSC140 DSP Core Reference Manual A-23Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDc,Dd ee Data Regi

A-24 SC140 DSP Core Reference ManualADDADD Add (DALU) ADDDescriptionThese operations add two source operands and store the result in a destination dat

ADDSC140 DSP Core Reference Manual A-25Example 2add d1,d0,d2The L2 bit is set from the 32-bit overflow. Note that the extension bits are in use in the

2-2 SC140 DSP Core Reference ManualArchitecture Overview.Figure 2-1. Block Diagram of the SC140 Core2.1.1 Data Arithmetic Logic Unit (DALU)The DALU

A-26 SC140 DSP Core Reference ManualADDInstruction FieldsDa,Db JJJJJ Data Register PairsDa,Da jj Data Register PairsDn FFF Single Source/Destination D

ADD2SC140 DSP Core Reference Manual A-27ADD2 Add Two 16-Bit Values (DALU) ADD2DescriptionStatus and Conditions that Affect InstructionNone.Status and

A-28 SC140 DSP Core Reference ManualADD2Instruction Formats and OpcodesInstruction FieldsDn FFF Single Source/Destination Data RegisterDa JJJ Single S

ADDASC140 DSP Core Reference Manual A-29ADDA Add (AGU) ADDADescriptionThese operations add an immediate signed 16-bit integer to the contents of a sou

A-30 SC140 DSP Core Reference ManualADDAExample 1adda r0,r1Example 2move.l #$8,mctl ;assigns m0 to r0, modulo arithmeticmove.l #$10,m0 ;puts modulo 16

ADDASC140 DSP Core Reference Manual A-31rx rrrr AGU Source RegisterRx RRRR AGU Source/Destination Register0000 N0 0100 — 1000 R0 1100 R40001 N1 0101 —

A-32 SC140 DSP Core Reference ManualADDL1AADDL1A Add With One-Bit Arithmetic Shift Left ADDL1A of Source Operand (AGU)DescriptionStatus and Conditions

ADDL1ASC140 DSP Core Reference Manual A-33Instruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination R

A-34 SC140 DSP Core Reference ManualADDL2AADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2Aof Source Operand (AGU)DescriptionStatus and Conditions

ADDL2ASC140 DSP Core Reference Manual A-35Instruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination R

Architecture OverviewSC140 DSP Core Reference Manual 2-3• MOVE.2L loads or stores two long words (64-bit).2.1.1.1 Data Register FileThe DALU registe

A-36 SC140 DSP Core Reference ManualADDNC.WADDNC.W Add Without Changing ADDNC.W the Carry Bit (DALU)DescriptionStatus and Conditions that Affect Instr

ADDNC.WSC140 DSP Core Reference Manual A-37Instruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/Des

A-38 SC140 DSP Core Reference ManualADRADR Add and Round (DALU) ADRDescriptionStatus and Conditions that Affect InstructionStatus and Conditions Chang

ADRSC140 DSP Core Reference Manual A-39Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDa JJJ Single Sour

A-40 SC140 DSP Core Reference ManualANDAND Bitwise AND (DALU) ANDDescriptionThese operations perform a "logical and" between the two source

ANDSC140 DSP Core Reference Manual A-41Status and Conditions Changed by InstructionExample 1and d2,d1Example 2and #$0ff2e,d2,d1Example 3and #$ff2e0000

A-42 SC140 DSP Core Reference ManualANDInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/Destina

ANDSC140 DSP Core Reference Manual A-43AND Bitwise AND with 16-Bit Immediate (BMU) ANDDescriptionStatus and Conditions that Affect InstructionNone.Sta

A-44 SC140 DSP Core Reference ManualANDInstruction Formats and OpcodesInstruction FieldsDR HHHH Data/Address RegisterInstruction Words Cycles Type Opc

AND.WSC140 DSP Core Reference Manual A-45AND.W Bitwise AND with 16-Bit Immediate (BMU) AND.WDescriptionThese operations read from memory, modify the r

2-4 SC140 DSP Core Reference ManualArchitecture OverviewThe AGU in the SC140 core has two address arithmetic units (AAU) to allow two address generati

A-46 SC140 DSP Core Reference ManualAND.WStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionNone.Exampleand.w #$

AND.WSC140 DSP Core Reference Manual A-47Instruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode1

A-48 SC140 DSP Core Reference ManualASLASL Arithmetic Shift Left ASLBy One Bit (DALU)DescriptionStatus and Conditions that Affect InstructionStatus an

ASLSC140 DSP Core Reference Manual A-49Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDa,Db JJJJJ Data R

A-50 SC140 DSP Core Reference ManualASL2AASL2A Arithmetic Shift Left ASL2ABy Two Bits (AGU)DescriptionStatus and Conditions that Affect InstructionSta

ASLASC140 DSP Core Reference Manual A-51ASLA Arithmetic Shift Left ASLABy One Bit (AGU)DescriptionStatus and Conditions that Affect InstructionStatus

A-52 SC140 DSP Core Reference ManualASLLASLL Multiple-Bit Arithmetic Shift Left (DALU) ASLLDescriptionThese operations shift the contents of Dn by the

ASLLSC140 DSP Core Reference Manual A-53Status and Conditions Changed by InstructionExample 1asll d0,d1Example 2asll d0,d1Register Address Bit Name De

A-54 SC140 DSP Core Reference ManualASLLInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDa JJJ Single Sou

ASLWSC140 DSP Core Reference Manual A-55ASLW Word Arithmetic Shift Left 16 Bits (DALU) ASLWDescriptionStatus and Conditions that Affect InstructionNon

Architecture OverviewSC140 DSP Core Reference Manual 2-52.1.3 Program Sequencer Unit (PSEQ)The PSEQ performs instruction fetch, instruction dispatch,

A-56 SC140 DSP Core Reference ManualASLWInstruction Formats and OpcodesInstruction FieldsDn FFF Single Source/Destination Data RegisterDa JJJ Single S

ASRSC140 DSP Core Reference Manual A-57ASR Arithmetic Shift Right ASRBy One Bit (DALU)DescriptionStatus and Conditions that Affect InstructionStatus

A-58 SC140 DSP Core Reference ManualASRInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDa JJJ Single Sou

ASRASC140 DSP Core Reference Manual A-59ASRA Arithmetic Shift Right ASRA By One Bit (AGU)DescriptionStatus and Conditions that Affect InstructionStatu

A-60 SC140 DSP Core Reference ManualASRRASRR Multiple-Bit Arithmetic Shift Right (DALU) ASRRDescriptionThis operation shifts the contents of Dn by N b

ASRRSC140 DSP Core Reference Manual A-61Status and Conditions Changed by InstructionExample 1asrr #$3,d5Example 2asrr d3,d5Register Address Bit Name D

A-62 SC140 DSP Core Reference ManualASRRSInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDa JJJ Single So

ASRWSC140 DSP Core Reference Manual A-63ASRW Word Arithmetic Shift Right 16 Bits (DALU) ASRWDescriptionStatus and Conditions that Affect InstructionNo

A-64 SC140 DSP Core Reference ManualASRWInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/Destin

BFSC140 DSP Core Reference Manual A-65BBF Branch If False (AGU) BFDescriptionStatus and Conditions that Affect InstructionStatus and Conditions Change

2-6 SC140 DSP Core Reference ManualDALU2.2 DALUThis section describes the architecture and operation of the DALU, the block where most of the arithm

A-66 SC140 DSP Core Reference ManualBFInstruction Formats and OpcodesInstruction Fieldsd2$0000 $0000pc$0006 $0016Instruction WordsCycles1Note 1: If th

MOVES.4FSC140 DSP Core Reference Manual A-67BFD Branch If False Using a Delay Slot (AGU) BFDDescriptionStatus and Conditions that Affect InstructionSt

A-68 SC140 DSP Core Reference ManualMOVES.4FInstruction Formats and OpcodesInstruction Fieldsd1$0000 $002Ad2$0000 $0000d4$0000 $001Apc$0006 $0016Instr

BMCHGSC140 DSP Core Reference Manual A-69BMCHG Bit-Masked Change a BMCHG16-Bit Operand (BMU)DescriptionThese operations use an unsigned 16-bit immedia

A-70 SC140 DSP Core Reference ManualBMCHG.WStatus and Conditions Changed by InstructionExamplebmchg #$f0f0,d1.hInstruction Formats and OpcodesInstruct

BMCHG.WSC140 DSP Core Reference Manual A-71#u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data

A-72 SC140 DSP Core Reference ManualBMCHG.WBMCHG.W Bit-Masked Change a BMCHG.W16-Bit Operand in Memory (BMU)DescriptionThese operations use an unsigne

BMCHG.WSC140 DSP Core Reference Manual A-73Examplebmchg.w #$661f,<$800cInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterRegi

A-74 SC140 DSP Core Reference ManualBMCHG.Ws16 AAAAAAAAAAAAAAAA 16-bit signed SP address offset

BMCLR;Instruction Set:BMCLRSC140 DSP Core Reference Manual A-75BMCLR Bit-Masked Clear a 16-Bit Operand (BMU) BMCLRDescriptionThese operations use an u

DALUSC140 DSP Core Reference Manual 2-7The DALU programming model is shown in Table 2-1. Register D0 refers to the entire 40-bit register, whereas D0.

A-76 SC140 DSP Core Reference ManualBMCLRStatus and Conditions Changed by InstructionExamplebmclr #$b646,d7.lInstruction Formats and OpcodesInstructio

BMCLRSC140 DSP Core Reference Manual A-77#u16 iiiiiiiiiiiiiiii 16-bit unsigned immediate data

A-78 SC140 DSP Core Reference ManualBMCLR.WBMCLR.W Bit-Masked Clear a BMCLR.W16-Bit Operand in Memory (BMU)DescriptionThese operations use an unsigned

BMCLR.WSC140 DSP Core Reference Manual A-79Instruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcod

A-80 SC140 DSP Core Reference ManualBMSETBMSET Bit-Masked Set a 16-Bit Operand (BMU) BMSETDescriptionThese operations use an unsigned 16-bit immediate

BMSETSC140 DSP Core Reference Manual A-81bmset #$2436,d1.lInstruction Formats and OpcodesInstruction FieldsC1 CCC Control RegistersDR HHHH Data/Addres

A-82 SC140 DSP Core Reference ManualBMSETBMSET.W Bit-Masked Set a BMSET.W16-Bit Operand in Memory (BMU)DescriptionThese operations use an unsigned 16-

BMSETSC140 DSP Core Reference Manual A-83Examplebmset.w #$f111,<$800cInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterRegist

A-84 SC140 DSP Core Reference ManualBMTSETBMTSET Bit-Masked Test and Set a BMTSET16-Bit Operand (BMU)DescriptionThese operations use an unsigned 16-bi

BMTSETSC140 DSP Core Reference Manual A-85Example 2bmtset #$4238,d4.lInstruction Formats and OpcodesInstruction FieldsDR HHHH Data/Address RegisterReg

iv SC140 DSP Core Reference Manual2.2.2.1 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-172.2

2-8 SC140 DSP Core Reference ManualDALU2.2.1.1 Data Registers (D0–D15)In this section, the D0–D15 data registers are referred to as Dn. They can be

A-86 SC140 DSP Core Reference ManualBMTSET.WBMTSET.W Bit-Masked Test and Set a BMTSET.W16-Bit Operand in Memory (BMU)DescriptionThese operations use a

BMTSET.WSC140 DSP Core Reference Manual A-87Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplebmtset.w #

A-88 SC140 DSP Core Reference ManualBMTSET.WInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opco

BMTSTCSC140 DSP Core Reference Manual A-89BMTSTC Bit-Masked Test a BMTSTC16-Bit Operand If Clear (BMU)DescriptionThese operations use an unsigned 16-b

A-90 SC140 DSP Core Reference ManualBMTSTCInstruction Formats and OpcodesInstruction FieldsC1 CCC Control RegistersDR HHHH Data/Address RegisterL7:D7$

BMTSTC.WSC140 DSP Core Reference Manual A-91BMTSTC.W Bit-Masked Test a BMTSTC.W16-Bit Operand in Memory If Clear (BMU)DescriptionThese operations use

A-92 SC140 DSP Core Reference ManualBMTSTC.WStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplebmtstc.w #

BMTSTC.WSC140 DSP Core Reference Manual A-93Instruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opco

A-94 SC140 DSP Core Reference ManualBMTSTSBMTSTS Bit-Masked Test a BMTSTS16-Bit Operand If Set (BMU)DescriptionThese operations use an unsigned 16-bit

BMTSTSSC140 DSP Core Reference Manual A-95Examplebmtsts #$24a6,d7.hInstruction Formats and OpcodesInstruction FieldsC1 CCC Control RegistersDR HHHH Da

DALUSC140 DSP Core Reference Manual 2-9A special case of the MOVE.L instruction is used for reading from or writing to the EXT portion of a data regis

A-96 SC140 DSP Core Reference ManualBMTSTS.WBMTSTS.W Bit-Masked Test a BMTSTS.W16-Bit Operand in Memory (BMU)DescriptionThese operations use an unsign

BMTSTS.WSC140 DSP Core Reference Manual A-97Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplebmtsts.w #

A-98 SC140 DSP Core Reference ManualBMTSTS.WInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opco

BRASC140 DSP Core Reference Manual A-99BRA Branch (AGU) BRADescriptionStatus and Conditions that Affect InstructionNone.Status and Conditions Changed

A-100 SC140 DSP Core Reference ManualBRAExamplebra _label2 ; disassembled: bra >*+$8nopnop_label2Instruction Formats and OpcodesInstruction FieldsR

BRADSC140 DSP Core Reference Manual A-101BRAD Branch Using a Delay Slot (AGU) BRADDescriptionStatus and Conditions that Affect InstructionNone.Status

A-102 SC140 DSP Core Reference ManualBRADInstruction Formats and OpcodesInstruction FieldsRegister/Memory Address Before Afterlbl3 (displacement)$0000

BREAKSC140 DSP Core Reference Manual A-103BREAK Terminate the Loop and Branch BREAK to an Address (AGU)DescriptionStatus and Conditions that Affect In

A-104 SC140 DSP Core Reference ManualBREAKInstruction Formats and OpcodesInstruction FieldsInstruction Words Cycles Type Opcode15 8 7 0BREAK label 2 4

BSRSC140 DSP Core Reference Manual A-105BSR Branch to Subroutine (AGU) BSRDescriptionStatus and Conditions that Affect InstructionStatus and Condition

2-10 SC140 DSP Core Reference ManualDALU.2.2.1.2 Multiply-Accumulate (MAC) UnitThe MAC unit is the arithmetic part of the ALU containing both a mult

A-106 SC140 DSP Core Reference ManualBSRInstruction Formats and OpcodesInstruction FieldsInstruction Words Cycles Type Opcode15 8 7 0BSR <label 1 4

BSRDSC140 DSP Core Reference Manual A-107BSRD Branch to Subroutine Using a Delay Slot (AGU) BSRDDescriptionStatus and Conditions that Affect Instructi

A-108 SC140 DSP Core Reference ManualBSRDInstruction Formats and OpcodesInstruction FieldsInstruction WordsCycles1Note 1: The branch uses 4 cycles min

BTSC140 DSP Core Reference Manual A-109BT Branch If True (AGU) BTDescriptionStatus and Conditions that Affect InstructionStatus and Conditions Changed

A-110 SC140 DSP Core Reference ManualBTInstruction Formats and OpcodesInstruction Fieldsd2$0000 $0000pc$0006 $0016Instruction WordsCycles1Note 1: If t

BTDSC140 DSP Core Reference Manual A-111BTD Branch If True Using a Delay Slot (AGU) BTDDescriptionStatus and Conditions that Affect InstructionStatus

A-112 SC140 DSP Core Reference ManualBTDInstruction Formats and OpcodesInstruction Fieldsd1$0035 $002Ad2$0000 $0000d4$0000 $001Apc$0006 $0016Instructi

CLBSC140 DSP Core Reference Manual A-113C-DCLB Count Leading Bits (DALU) CLBDescriptionStatus and Conditions that Affect InstructionNone.Status and Co

A-114 SC140 DSP Core Reference ManualCLBInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/Destin

CLRSC140 DSP Core Reference Manual A-115CLR Clear a Data Register (DALU) CLRDescriptionStatus and Conditions that Affect InstructionNone.Status and Co

DALUSC140 DSP Core Reference Manual 2-11DECEQ Decrement a data register and set T (the true bit) if zeroDECGE Decrement a data register and set T if g

A-116 SC140 DSP Core Reference ManualCLRInstruction FieldsDn FFF Destination Data RegisterDa JJJJJ Source Data RegisterDa jj Source Data Register000 D

CMPEQSC140 DSP Core Reference Manual A-117CMPEQ Compare for Equal (DALU) CMPEQDescriptionStatus and Conditions that Affect InstructionNone.Status and

A-118 SC140 DSP Core Reference ManualCMPEQDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 101 D5 111 D7Note: Th

CMPEQ.WSC140 DSP Core Reference Manual A-119CMPEQ.W Compare for Equal (DALU) CMPEQ.WDescriptionStatus and Conditions that Affect InstructionNone.Statu

A-120 SC140 DSP Core Reference ManualCMPEQ.WInstruction Formats and OpcodesInstruction FieldsDn FFF Single Source/Destination Data RegisterInstructio

CMPEQASC140 DSP Core Reference Manual A-121CMPEQA Compare for Equal (AGU) CMPEQADescriptionStatus and Conditions that Affect InstructionStatus and Con

A-122 SC140 DSP Core Reference ManualCMPEQAInstruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination

CMPGTSC140 DSP Core Reference Manual A-123CMPGT Compare for Greater Than (DALU) CMPGTDescriptionStatus and Conditions that Affect InstructionNone.Stat

A-124 SC140 DSP Core Reference ManualCMPGTDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 101 D5 111 D7Note: T

CMPGT.WSC140 DSP Core Reference Manual A-125CMPGT.W Compare for Greater Than CMPGT.W (DALU)DescriptionThese instructions set the T bit if the content

2-12 SC140 DSP Core Reference ManualDALU2.2.1.3 Bit-Field Unit (BFU)The BFU is the logic part of the ALU. It contains a 40-bit parallel bidirectiona

A-126 SC140 DSP Core Reference ManualCMPGT.WInstruction Formats and OpcodesInstruction FieldsDn FFF Single Source/Destination Data RegisterInstructio

CMPGTASC140 DSP Core Reference Manual A-127CMPGTA Compare for Greater Than (AGU) CMPGTADescriptionStatus and Conditions that Affect InstructionStatus

A-128 SC140 DSP Core Reference ManualCMPGTAInstruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination

CMPHISC140 DSP Core Reference Manual A-129CMPHI Unsigned Compare for Higher (DALU) CMPHIDescriptionStatus and Conditions that Affect InstructionNone.

A-130 SC140 DSP Core Reference ManualCMPHIDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 101 D5 111 D7Note: T

CMPHIASC140 DSP Core Reference Manual A-131CMPHIA Unsigned Compare for Higher (AGU) CMPHIADescriptionStatus and Conditions that Affect InstructionStat

A-132 SC140 DSP Core Reference ManualCMPHIAInstruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination

CONTSC140 DSP Core Reference Manual A-133CONT Continue to the Next Loop Iteration (AGU) CONTDescriptionStatus and Conditions that Affect InstructionSt

A-134 SC140 DSP Core Reference ManualCONTInstruction Formats and OpcodesInstruction FieldsInstruction WordsCycles1Note 1: If LC > 1, CONT uses 3 cy

CONTDSC140 DSP Core Reference Manual A-135CONTD Continue to Next Loop Iteration CONTDUsing a Delay Slot (AGU)DescriptionStatus and Conditions that Aff

DALUSC140 DSP Core Reference Manual 2-13 2.2.1.4 Data Shifter/LimiterThe data shifters/limiters provide special post-processing on data written from

A-136 SC140 DSP Core Reference ManualCONTDInstruction Formats and OpcodesInstruction Fieldsloopend0lbl3 add d0,d1,d2Instruction WordsCycles1Note 1: If

DEBUGSC140 DSP Core Reference Manual A-137DEBUG Enter Debug Mode (AGU) DEBUGDescriptionStatus and Conditions that Affect InstructionNoneStatus and Con

A-138 SC140 DSP Core Reference ManualDEBUGEVDEBUGEV Signal a Debug Event (AGU) DEBUGEVDescriptionStatus and Conditions that Affect InstructionNone.Sta

DECASC140 DSP Core Reference Manual A-139DECA Decrement a Register (AGU) DECADescriptionStatus and Conditions that Affect InstructionStatus and Condit

A-140 SC140 DSP Core Reference ManualDECA#u5 iiiii 5-bit unsigned immediate data = 1, set by the assembler

DECEQSC140 DSP Core Reference Manual A-141DECEQ Decrement and Set T If Equal Zero (DALU) DECEQDescriptionStatus and Conditions that Affect Instruction

A-142 SC140 DSP Core Reference ManualDECEQInstruction FieldsDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 10

DECEQASC140 DSP Core Reference Manual A-143DECEQA Decrement and Set T If Equal Zero DECEQA(AGU)DescriptionStatus and Conditions that Affect Instructio

A-144 SC140 DSP Core Reference ManualDECGEDECGE Decrement and Set T DECGEIf Greater Than or Equal to Zero (DALU)DescriptionStatus and Conditions that

DECGESC140 DSP Core Reference Manual A-145Instruction FieldsDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 10

2-14 SC140 DSP Core Reference ManualDALU2.2.1.5 ScalingThe data shifters in the shifter/limiter unit can perform the following data shift operations

A-146 SC140 DSP Core Reference ManualDECGEADECGEA Decrement and Set T DECGEAIf Greater Than or Equal to Zero (AGU)DescriptionStatus and Conditions tha

DECGEASC140 DSP Core Reference Manual A-147Instruction Formats and OpcodesInstruction FieldsRx RRRR AGU Source/Destination RegisterInstruction Words C

A-148 SC140 DSP Core Reference ManualDIDI Disable Interrupts (AGU) DIDescriptionStatus and Conditions that Affect InstructionStatus and Conditions Cha

DISC140 DSP Core Reference Manual A-14915 8 7 0DI 1 1 4 1001111101111101

A-150 SC140 DSP Core Reference ManualDIVDIV Divide Iteration (DALU) DIVDescriptionOperation Assembler SyntaxIf Dn[39] ⊕ Da[39] = 1,then 2 * Dn + C + (

DIVSC140 DSP Core Reference Manual A-151Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplediv d2,d13. Ca

A-152 SC140 DSP Core Reference ManualDIVInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDn FFF Single Sou

DMACSSSC140 DSP Core Reference Manual A-153DMACSS Multiply Signed By Signed and DMACSS Accumulate With Right Shifted Data Register (DALU)DescriptionSt

A-154 SC140 DSP Core Reference ManualDMACSSInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDc,Dd ee Data

DMACSUSC140 DSP Core Reference Manual A-155DMACSU Multiply Signed By Unsigned and DMACSUAccumulate With Right Shifted Data Register (DALU)DescriptionS

DALUSC140 DSP Core Reference Manual 2-15 The Ln bit is calculated (and set or cleared) for the following saturable instructions: ABS, ADC, ADR, ADD, A

A-156 SC140 DSP Core Reference ManualDMACSUInstruction FieldsDc,Dd ee Data Register PairsDn FFF Single Source/Destination Data Register00 D0,D1 01 D2,

DOENnSC140 DSP Core Reference Manual A-157DOENn DO Enable Long Loop (AGU) DOENnDescriptionThis instruction initializes the selected loop as a long loo

A-158 SC140 DSP Core Reference ManualDOENnInstruction Formats and OpcodesInstruction Fieldsn Loop IdentifierDR HHHH Data/Address RegisterInstruction W

DOENSHnSC140 DSP Core Reference Manual A-159DOENSHn Do Enable Short Loop (AGU) DOENSHnDescriptionThis instruction initializes the selected loop as a s

A-160 SC140 DSP Core Reference ManualDOENSHnInstruction Formats and OpcodesInstruction Fieldsn Loop IdentifierDR HHHH Data/Address RegisterSR$00E4 000

DOSETUPnSC140 DSP Core Reference Manual A-161DOSETUPn Setup Long Loop DOSETUPnStart Address (AGU)DescriptionStatus and Conditions that Affect Instruc

A-162 SC140 DSP Core Reference ManualDOSETUPnInstruction Formats and OpcodesInstruction Fieldsn Loop IdentifierInstruction Words Cycles Type Opcode15

EISC140 DSP Core Reference Manual A-163E-JEI Enable Interrupts (AGU) EIDescriptionStatus and Conditions that Affect InstructionStatus and Conditions C

A-164 SC140 DSP Core Reference ManualEI

EORSC140 DSP Core Reference Manual A-165EOR Bitwise Exclusive OR (DALU) EORDescriptionStatus and Conditions that Affect InstructionNone.Status and Con

2-16 SC140 DSP Core Reference ManualDALUNote that in the unusual case where arithmetic saturation mode is set between a DALU instruction and a subsequ

A-166 SC140 DSP Core Reference ManualEORInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/Destin

EORSC140 DSP Core Reference Manual A-167EOR Bitwise Exclusive OR on a 16-Bit Operand (BMU) EORDescriptionStatus and Conditions that Affect Instruction

A-168 SC140 DSP Core Reference ManualEORInstruction Formats and OpcodesInstruction FieldsDR HHHH Data/Address RegisterInstruction Words Cycles Type Op

EOR.WSC140 DSP Core Reference Manual A-169EOR.W Bitwise Exclusive OR on EOR.W a 16-Bit Operand in Memory (BMU)DescriptionThese operations read from me

A-170 SC140 DSP Core Reference ManualEOR.WExampleeor.w #$aaaa,(r0)Instruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterRegister/Mem

EXTRACTSC140 DSP Core Reference Manual A-171EXTRACT Extract Signed Bit Field (DALU) EXTRACTDescriptionThese operations extract a bit field from a sour

A-172 SC140 DSP Core Reference ManualEXTRACTInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/De

EXTRACTUSC140 DSP Core Reference Manual A-173EXTRACTU Extract Unsigned Bit Field EXTRACTU(DALU)DescriptionThese operations extract a bit field from a

A-174 SC140 DSP Core Reference ManualEXTRACTUInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/D

IADDNC.WSC140 DSP Core Reference Manual A-175IADDNC.W Integer Addition IADDNC.WWithout Changing the Carry BitNot Affected by Saturation (DALU)Descri

DALUSC140 DSP Core Reference Manual 2-17The following table (Table 2-11) shows the arithmetic saturation and rounding operations for the four possible

A-176 SC140 DSP Core Reference ManualIFcIFc Conditionally Execute a Group or Subgroup (PREFIX) IFcDescriptionThese instructions add conditional contro

IFcSC140 DSP Core Reference Manual A-177Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionNone.Exampleift move.

A-178 SC140 DSP Core Reference ManualILLEGALILLEGAL Generate an Illegal Exception ILLEGALRequest (AGU)DescriptionOperation Assembler Syntaxupon servic

ILLEGALSC140 DSP Core Reference Manual A-179Status and Conditions that Affect InstructionNone.Status and Conditions Changed by InstructionExampleilleg

A-180 SC140 DSP Core Reference ManualIMACIMAC Integer Multiply-Accumulate (DALU) IMACDescriptionStatus and Conditions that Affect InstructionNone.Sta

IMACSC140 DSP Core Reference Manual A-181–5 $FFFBx 3$0003–15 $000F+8$0008–7 $FFF9Example 2imac -d4,d5,d6–42 $002Ax 11 $000B–462 $FE32+4096$10003,634 $

A-182 SC140 DSP Core Reference ManualIMACDa,Db JJJJJ Data Register PairsDa,Da jj Data Register PairsDn FFF Single Source/Destination Data Register0000

IMACLHUUSC140 DSP Core Reference Manual A-183IMACLHUU Integer Multiply-Accumulate IMACLHUU Lower Unsigned By Upper Unsigned (DALU)DescriptionStatus an

A-184 SC140 DSP Core Reference ManualIMACLHUUInstruction Formats and OpcodesInstruction FieldsDa jjj Single Source/Destination Data RegisterDb JJJ Sin

IMACUSSC140 DSP Core Reference Manual A-185IMACUS Integer Multiply Accumulate IMACUSUnsigned By Signed (DALU)DescriptionStatus and Conditions that Aff

SC140 DSP Core Reference Manual vChapter 3Control Registers3.1 Core Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-18 SC140 DSP Core Reference ManualDALUFigure 2-3. DALU Data Representations2.2.2.2 Data FormatsThree types of two’s complement data formats are

A-186 SC140 DSP Core Reference ManualIMACUS2 $0002x –64$FFC0–128 $FF80+0$0000-128 $FF80Instruction Formats and OpcodesInstruction FieldsDa jjj Single

IMPYSC140 DSP Core Reference Manual A-187IMPY Integer Multiply (DALU) IMPYDescriptionStatus and Conditions that Affect InstructionNone.Status and Con

A-188 SC140 DSP Core Reference ManualIMPYInstruction FieldsDa,Da jj Data Register PairsDa,Db JJJJJ Data Register PairsDn FFF Single Source/Destination

IMPY.WSC140 DSP Core Reference Manual A-189IMPY.W Signed Immediate Integer Multiply (DALU) IMPY.WDescriptionStatus and Conditions that Affect Instruct

A-190 SC140 DSP Core Reference ManualIMPY.W–8 $FFF8x –2$FFFE+16 $0010Instruction Formats and OpcodesInstruction FieldsDn FFF Single Source/Destination

IMPYHLUUSC140 DSP Core Reference Manual A-191IMPYHLUU Integer Multiply Upper IMPYHLUUUnsigned By Lower Unsigned (DALU)DescriptionStatus and Conditions

A-192 SC140 DSP Core Reference ManualIMPYHLUUInstruction Formats and OpcodesInstruction FieldsDa jjj Single Source/Destination Data RegisterDb JJJ Sin

IMPYSUSC140 DSP Core Reference Manual A-193IMPYSU Integer Multiply IMPYSUSigned By Unsigned (DALU)DescriptionStatus and Conditions that Affect Instruc

A-194 SC140 DSP Core Reference ManualIMPYSUInstruction Formats and OpcodesInstruction FieldsDa jjj Single Source/Destination Data RegisterDb JJJ Singl

IMPYUUSC140 DSP Core Reference Manual A-195IMPYUU Integer Multiply IMPYUUUnsigned By Unsigned (DALU)DescriptionStatus and Conditions that Affect Instr

DALUSC140 DSP Core Reference Manual 2-192.2.2.2.2 Signed IntegerThis format is used when processing data as integers. Using this format, the N-bit o

A-196 SC140 DSP Core Reference ManualIMPYUUDb JJJ Single Source Data RegisterDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6

INCSC140 DSP Core Reference Manual A-197INC Increment a Data Register By One (DALU) INCDescriptionStatus and Conditions that Affect InstructionStatus

A-198 SC140 DSP Core Reference ManualINCExample 2inc d15Arithmetic saturation mode set, SR[2], 32-bit overflow indicated in EMR[2].Instruction Formats

INC.FSC140 DSP Core Reference Manual A-199INC.F Increment HP of a Data Register by One (DALU) INC.FDescriptionStatus and Conditions that Affect Instru

A-200 SC140 DSP Core Reference ManualINC.FInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDn FFF Single S

INCASC140 DSP Core Reference Manual A-201INCA Increment Register (AGU) INCADescriptionStatus and Conditions that Affect InstructionStatus and Conditio

A-202 SC140 DSP Core Reference ManualINCAInstruction Formats and OpcodesInstruction FieldsRx RRRR AGU Source/Destination RegisterInstruction Words Cyc

INSERTSC140 DSP Core Reference Manual A-203INSERT Insert Bit Field (DALU) INSERTDescriptionThese operations insert a bit field from a source data regi

A-204 SC140 DSP Core Reference ManualINSERTInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDb jjj Single Source/Des

JFSC140 DSP Core Reference Manual A-205JF Jump If False (AGU) JFDescriptionIf the T bit is cleared, program execution continues at a specified 32-bit

2-20 SC140 DSP Core Reference ManualDALU2.2.2.3 MultiplicationMost of the operations are performed identically in fractional and integer arithmetic.

A-206 SC140 DSP Core Reference ManualJFInstruction Formats and OpcodesInstruction FieldsRn RRR Address Registerd1$00 0000 0000 $00 0000 0029d2$00 0000

JFDSC140 DSP Core Reference Manual A-207JFD Jump If False Using a Delay Slot (AGU) JFDDescriptionIf the T bit is cleared, program execution continues

A-208 SC140 DSP Core Reference ManualJFDInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterRegister/Memory Address Before AfterSR

JFDSC140 DSP Core Reference Manual A-209JMP Jump (AGU) JMPDescriptionThese operations continue program execution at a specified 32-bit memory destinat

A-210 SC140 DSP Core Reference ManualJFDInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode15

JMPDSC140 DSP Core Reference Manual A-211JMPD Jump Using a Delay Slot (AGU) JMPDDescriptionStatus and Conditions that Affect InstructionNone.Status an

A-212 SC140 DSP Core Reference ManualJMPDInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode1

JSRSC140 DSP Core Reference Manual A-213JSR Jump to Subroutine (AGU) JSRDescriptionThese operations jump to the subroutine location in program memory

A-214 SC140 DSP Core Reference ManualJSRInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode15

JSRDSC140 DSP Core Reference Manual A-215JSRD Jump to a Subroutine Using a Delay Slot (AGU) JSRDDescriptionExecutes the execution set in the delay slo

DALUSC140 DSP Core Reference Manual 2-212.2.2.5.2 Unsigned ComparisonWhen performing an unsigned comparison, the condition code computation is diffe

A-216 SC140 DSP Core Reference ManualJSRDInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode1

JTSC140 DSP Core Reference Manual A-217JT Jump If True (AGU) JTDescriptionIf the T bit is set, these operations continue program execution at a specif

A-218 SC140 DSP Core Reference ManualJTInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode15

JTDSC140 DSP Core Reference Manual A-219JTD Jump If True Using Delay Slot (AGU) JTDDescriptionIf the T bit is set, this instruction continues program

A-220 SC140 DSP Core Reference ManualJTDInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode15

LPMARKxSC140 DSP Core Reference Manual A-221L-MLPMARKx End-of-Loop Mark (PREFIX) LPMARKxDescriptionThe LPMARK prefix bits are used for hardware loops

A-222 SC140 DSP Core Reference ManualLPMARKxLPMARKBFor long loops (SLF=0), this prefix bit is placed at LA-2 (two sets before the last set of the loop

LPMARKxSC140 DSP Core Reference Manual A-223Status and Conditions Changed by LPMARK ExecutionThe loop flag (LFn) and short loop flag (SLFn) are cleare

A-224 SC140 DSP Core Reference ManualLSLLLSLL Multiple-Bit Bitwise Shift Left (DALU) LSLLDescriptionStatus and Conditions that Affect InstructionNone.

LSLLSC140 DSP Core Reference Manual A-225Example 2lsll d4,d2Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction Fie

2-22 SC140 DSP Core Reference ManualDALUFigure 2-5 shows the four cases for rounding a number in the Dn.h register. If scaling is set in the SR, the r

A-226 SC140 DSP Core Reference ManualLSRLSR Bitwise Shift Right One Bit (DALU) LSRDescriptionStatus and Conditions that Affect InstructionNone.Status

LSRASC140 DSP Core Reference Manual A-227LSRA Bitwise Shift Right By One Bit (AGU) LSRADescriptionStatus and Conditions that Affect InstructionStatus

A-228 SC140 DSP Core Reference ManualLSRRLSRR Multiple-Bit Bitwise Shift Right (DALU) LSRR|DescriptionStatus and Conditions that Affect InstructionNon

LSRRSC140 DSP Core Reference Manual A-229Status and Conditions Changed by InstructionExample 1lsrr d4,d2Example 2lsrr d4,d2Register Address Bit Name D

A-230 SC140 DSP Core Reference ManualLSRRInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/Dest

LSRWSC140 DSP Core Reference Manual A-231LSRW Word Bitwise Shift Right (DALU) LSRWDescriptionStatus and Conditions that Affect InstructionNone.Status

A-232 SC140 DSP Core Reference ManualLSRWInstruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/D

MACSC140 DSP Core Reference Manual A-233MAC Signed Fractional Multiply-Accumulate (DALU) MACDescriptionThese operations perform signed fractional mult

A-234 SC140 DSP Core Reference ManualMAC0.001 $1000x 0.011$30000.0000110$0600+0.1000000$40000.1000110$4600Example 2mac #$1000,d5,d6Instruction Formats

MACSC140 DSP Core Reference Manual A-235Da JJJ Single Source Data RegisterDa,Db JJJJJ Data Register PairsDa,Da jj Data Register PairsDn FFF Single

DALUSC140 DSP Core Reference Manual 2-232.2.2.6.2 Two’s Complement RoundingWhen two’s complement rounding is selected by setting the rounding mode (

A-236 SC140 DSP Core Reference ManualMACRMACR Signed Fractional Multiply-Accumulate MACRand Round (DALU)DescriptionStatus and Conditions that Affect I

MACRSC140 DSP Core Reference Manual A-2370.000 0000 1000$0080x 0.000 0000 1000$00800.000 0000 0000 0000 1000$000080000+0.000 0000 0000 0111 0000$0007r

A-238 SC140 DSP Core Reference ManualMACRDa,Da jj Data Register PairsDn FFF Single Source/Destination Data Register00 D1,D1 01 D3,D3 10 D5,D5 11 D7,

MACSUSC140 DSP Core Reference Manual A-239MACSU Fractional Multiply-Accumulate MACSUSigned By Unsigned (DALU)DescriptionStatus and Conditions that Aff

A-240 SC140 DSP Core Reference ManualMACSU1.100 $C000x 0.000 0000 0000 0001$0001 (2–15)1.111 1111 1111 1111 1000$FFFF 8000Instruction Formats and Opco

MACUSSC140 DSP Core Reference Manual A-241MACUS Fractional Multiply-Accumulate MACUSUnsigned By Signed (DALU)DescriptionStatus and Conditions that Af

A-242 SC140 DSP Core Reference ManualMACUSInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDc,Dd ee Data R

MACUUSC140 DSP Core Reference Manual A-243MACUU Fractional Multiply-Accumulate MACUUUnsigned By Unsigned (DALU)DescriptionStatus and Conditions that

A-244 SC140 DSP Core Reference ManualMACUUInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDc,Dd ee Data R

MARKSC140 DSP Core Reference Manual A-245MARK Push the PC into the Trace Buffer (AGU) MARKDescriptionStatus and Conditions that Affect InstructionNone

2-24 SC140 DSP Core Reference ManualDALUFigure 2-6 shows the four cases for rounding a number in the Dn.h register. If scaling is set in the SR, the r

A-246 SC140 DSP Core Reference ManualMAXMAX Transfer Maximum Signed Value (DALU) MAXDescriptionStatus and Conditions that Affect InstructionNone.Statu

MAX2SC140 DSP Core Reference Manual A-247MAX2 Transfer Two 16-Bit MAX2Maximum Signed Values (DALU)DescriptionStatus and Conditions that Affect Instruc

A-248 SC140 DSP Core Reference ManualMAX2Instruction FieldsDg,Dh GG Data Register Pairs00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7Note: This instruction can s

MAX2VITSC140 DSP Core Reference Manual A-249MAX2VIT MAX2 MAX2VITfor Viterbi Kernel (DALU)DescriptionThese operations independently compare the 16-bi

A-250 SC140 DSP Core Reference ManualMAX2VITStatus and Conditions Changed by InstructionExamplemax2vit d4,d2Instruction Formats and OpcodesNote: This

MAXMSC140 DSP Core Reference Manual A-251MAXM Transfer Maximum Absolute Value (DALU) MAXMDescriptionStatus and Conditions that Affect InstructionNone.

A-252 SC140 DSP Core Reference ManualMAXMInstruction FieldsDg,Dh GG Data Register Pairs00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7Note: This instruction can s

MINSC140 DSP Core Reference Manual A-253MIN Transfer Minimum Signed Value (DALU) MINDescriptionStatus and Conditions that Affect InstructionNone.Statu

A-254 SC140 DSP Core Reference ManualMIN2MOVE.2F Move Two Fractional Words from MOVE.2FMemory to a Register Pair (AGU)DescriptionStatus and Conditions

MOVE.2FSC140 DSP Core Reference Manual A-255Instruction Formats and OpcodesNotes: 1. ** indicates serial grouping encoding.2. When the form (Rn + N0)

DALUSC140 DSP Core Reference Manual 2-252.2.2.7 Arithmetic Saturation ModeBy setting the arithmetic saturation mode (SM) bit in the SR, the arithmet

A-256 SC140 DSP Core Reference ManualMOVE.2LMOVE.2L Move Two Integer Longs MOVE.2Lto/from a Register Pair (AGU)DescriptionThese operations move two lo

MOVE.2LSC140 DSP Core Reference Manual A-257Instruction Formats and OpcodesInstruction Fieldsw Read/Write NotationDa:Db hh Data Register PairsEA MMM E

A-258 SC140 DSP Core Reference ManualMOVE.2WMOVE.2W Move Two Integer Words MOVE.2Wto/from a Register Pair (AGU)DescriptionStatus and Conditions that A

MOVE.2WSC140 DSP Core Reference Manual A-259Instruction Formats and OpcodesNotes: 1. ** indicates serial grouping encoding.2. When the form (Rn + N0)

A-260 SC140 DSP Core Reference ManualMOVE.4FMOVE.4F Move Four Fractional Words from MOVE.4FMemory to a Register Quad (AGU)DescriptionStatus and Condit

MOVE.4FSC140 DSP Core Reference Manual A-261move.4f (r0),d0:d1:d2:d3Instruction Formats and OpcodesNotes: 1. ** indicates serial grouping encoding.2.

A-262 SC140 DSP Core Reference ManualMOVE.4WMOVE.4W Move Four Integer Words MOVE.4Wto/from a Register Quad (AGU)DescriptionStatus and Conditions that

MOVE.4WSC140 DSP Core Reference Manual A-263move.4w d0:d1:d2:d3,(r0)Instruction Formats and OpcodesInstruction Fieldsw Read/Write NotationDa:Db:Dc:Dd

A-264 SC140 DSP Core Reference ManualMOVE.BMOVE.B Byte Move (AGU) MOVE.BDescriptionThese operations move 8-bit data from memory to a data or address r

MOVE.BSC140 DSP Core Reference Manual A-265Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemove.b d3,(

2-26 SC140 DSP Core Reference ManualDALU2.2.2.8 Multi-Precision Arithmetic SupportThe SC140 DALU supports multi-precision arithmetic for fractional

A-266 SC140 DSP Core Reference ManualMOVE.BInstruction Formats and OpcodesInstruction FieldsDR HHHH Data/Address RegisterInstruction Words Cycles Type

MOVE.BSC140 DSP Core Reference Manual A-267Rn RRR Address Registerea MM Effective Address Notation000 R0 010 R2 100 R4 110 R6001 R1 011 R3 101 R5 111

A-268 SC140 DSP Core Reference ManualMOVE.FMOVE.F Move Fractional Word MOVE.Fto/from Memory (AGU)DescriptionThese operations read a fractional word fr

MOVE.FSC140 DSP Core Reference Manual A-269Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemove.f ($54

A-270 SC140 DSP Core Reference ManualMOVE.FInstruction Formats and OpcodesNotes: 1. ** indicates serial grouping encoding.2. When the form (Rn + N0) i

MOVE.FSC140 DSP Core Reference Manual A-271ea MM Effective Address NotationRn RRR Address Register00(Rn)+01(Rn)–10(Rn+N0)11(Rn)000 R0 010 R2 100 R4 11

A-272 SC140 DSP Core Reference ManualMOVE.LMOVE.L Move Long Word (AGU) MOVE.LDescriptionThese operations move an immediate long word (32-bit data) int

MOVE.LSC140 DSP Core Reference Manual A-273Instruction FieldsC1 CCC Control RegistersC2 CCCC General RegistersC4 DDDDD General RegistersDb jjj Single

A-274 SC140 DSP Core Reference ManualMOVE.Lw Read/Write Notation0write1read#s32 (31)IIIIIIIIIIIIIIII(16)(15)iiiiiiiiiiiiiiii (0)32-bit signed immediat

MOVE.LSC140 DSP Core Reference Manual A-275MOVE.L Move Long Register Extensions (AGU) MOVE.LDescriptionThese six operations save (restore) the extensi

DALUSC140 DSP Core Reference Manual 2-27Figure 2-8 illustrates the use of these instructions in the case of a double-precision multiplication of 32-bi

A-276 SC140 DSP Core Reference ManualMOVE.LStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemove.l d0.e

MOVE.LSC140 DSP Core Reference Manual A-277Instruction Formats and OpcodesInstruction FieldsDe QQ Data RegisterDo qq Data RegisterDa.E:Db.E ff Data Re

A-278 SC140 DSP Core Reference ManualMOVE.La32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute long address

MOVE.LSC140 DSP Core Reference Manual A-279MOVE.L Move Long (AGU) MOVE.LDescriptionThese operations move a signed long word (32-bit data) from memory

A-280 SC140 DSP Core Reference ManualMOVE.LMOVE.L (a32),DRMOVE.L DR,(a32)Moves a 32-bit long word between a data or address register and a memory addr

MOVE.LSC140 DSP Core Reference Manual A-281Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemove.l d0,(

A-282 SC140 DSP Core Reference ManualMOVE.LMOVE.L DR,(Rn+u3)15 8 7 0MOVE.L (Rn+s15),DR 2 2 3 0 0 0wHHHH1 s s 0 0RRRMOVE.L DR,(Rn+s15) 100sssssssssssss

MOVE.LSC140 DSP Core Reference Manual A-283Instruction FieldsC3 DDDD General RegistersC4 DDDDD General RegistersDR HHHH Data/Address RegisterEA MMM Ef

A-284 SC140 DSP Core Reference ManualMOVE.La16 AAAAAAAAAAAAAAAA 16-bit unsigned absolute addressa32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute l

MOVE.WSC140 DSP Core Reference Manual A-285MOVE.W Move Immediate Integer Word (AGU) MOVE.WDescriptionThese operations move a signed immediate integer

vi SC140 DSP Core Reference Manual4.6.4 General EOnCE Register Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-344.7 EOn

2-28 SC140 DSP Core Reference ManualDALUFigure 2-9 illustrates the use of the fractional multiplication and multiply-accumulate instructions in the ca

A-286 SC140 DSP Core Reference ManualMOVE.WStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemove.w #$00

MOVE.WSC140 DSP Core Reference Manual A-287Instruction Formats and OpcodesInstruction FieldsC4 DDDDD General RegistersInstruction Words Cycles Type Op

A-288 SC140 DSP Core Reference ManualMOVE.WDR HHHH Data/Address RegisterRn RRR Address Register0000 D0 0100 D4 1000 R0 1100 R40001 D1 0101 D5 1001 R1

MOVE.WSC140 DSP Core Reference Manual A-289MOVE.W Move Integer Word (AGU) MOVE.WDescriptionThese operations either read a signed integer word from mem

A-290 SC140 DSP Core Reference ManualMOVE.WMOVE.W (Rn+u3),DRMOVE.W DR,(Rn+u3)Moves a signed word between a data or address register (DR) and a memory

MOVE.WSC140 DSP Core Reference Manual A-291Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemove.w d1,(

A-292 SC140 DSP Core Reference ManualMOVE.WInstruction Formats and OpcodesInstruction Words Cycles Type Opcode15 8 7 0MOVE.W (a32),DR 3 1 3 0000HHHHAA

MOVE.WSC140 DSP Core Reference Manual A-293Instruction Fieldsw Read/Write NotationC3 DDDD General RegistersC4 DDDDD General RegistersDR HHHH Data/Addr

A-294 SC140 DSP Core Reference ManualMOVE.Wa16 AAAAAAAAAAAAAAAA 16-bit unsigned absolute addressa32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute l

MOVEcSC140 DSP Core Reference Manual A-295MOVEc Conditional Address Register Move (AGU) MOVEcDescriptionThis instruction conditionally copies the valu

DALUSC140 DSP Core Reference Manual 2-29Figure 2-10 illustrates the use of these instructions in the case of a signed integer double-precision multipl

A-296 SC140 DSP Core Reference ManualMOVEcInstruction Formats and OpcodesInstruction FieldsRq qqq Address RegisterRn RRR Address RegisterInstruction W

MOVES.2FSC140 DSP Core Reference Manual A-297MOVES.2F Move Two Fractional Words to MOVES.2FMemory With Scaling andSaturation (AGU)DescriptionThe data

A-298 SC140 DSP Core Reference ManualMOVES.2FThe Ln bit is set in d0, and the number in d0 is positive (bit 39 = 0), so the saturated value $7FFF is w

MOVES.4FSC140 DSP Core Reference Manual A-299MOVES.4F Move Four Fractional Words to MOVES.4FMemory With Scaling and Saturation (AGU)DescriptionThe dat

A-300 SC140 DSP Core Reference ManualMOVES.4FInstruction Formats and OpcodesNotes: 1. ** indicates serial grouping encoding.2. When the form (Rn + N0)

MOVES.FSC140 DSP Core Reference Manual A-301MOVES.F Move Fractional Word to MOVES.FMemory With Scaling and Saturation (AGU)DescriptionThis operation m

A-302 SC140 DSP Core Reference ManualMOVES.4FStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemoves.f d

MOVES.4FSC140 DSP Core Reference Manual A-303Instruction Formats and OpcodesInstruction FieldsDb jjj Single Source/Destination Data RegisterEA MMM E

A-304 SC140 DSP Core Reference ManualMOVES.4Fs15 sssssssssssssss Signed 15-bit offset

MOVES.LSC140 DSP Core Reference Manual A-305MOVES.L Move Long to MOVES.LMemory With Scaling and Saturation (AGU)DescriptionThe data is scaled accordin

2-30 SC140 DSP Core Reference ManualDALUFigure 2-11 illustrates the use of these instructions in the case of an unsigned integer double-precision mult

A-306 SC140 DSP Core Reference ManualMOVES.LInstruction Formats and OpcodesNotes: 1. ** indicates serial grouping encoding.2. When the form (Rn + N0)

MOVEU.BSC140 DSP Core Reference Manual A-307MOVEU.B Move Unsigned Byte from MOVEU.BMemory (AGU)DescriptionThese operations move an unsigned byte fro

A-308 SC140 DSP Core Reference ManualMOVEU.BStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemoveu.b ($

MOVEU.BSC140 DSP Core Reference Manual A-309Instruction Formats and OpcodesInstruction FieldsDR HHHH Data/Address Registerea MM Effective Address Nota

A-310 SC140 DSP Core Reference ManualMOVEU.Ba32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32-bit absolute long addresss15 sssssssssssssss Signed 15-bit offset

MOVEU.LSC140 DSP Core Reference Manual A-311MOVEU.L Move Unsigned Immediate Long MOVEU.Lto a Data Register (AGU)Description Status and Conditions tha

A-312 SC140 DSP Core Reference ManualMOVEU.LInstruction Formats and OpcodesInstruction FieldsDb jjj Single Source/Destination Data RegisterInstructi

MOVEU.WSC140 DSP Core Reference Manual A-313MOVEU.W Move Unsigned Immediate Word MOVEU.Wto a Register Portion (AGU)DescriptionThese operations move an

A-314 SC140 DSP Core Reference ManualMOVEU.WInstruction Formats and OpcodesInstruction FieldsDb jjj Single Source/Destination Data RegisterInstructi

MOVEU.WSC140 DSP Core Reference Manual A-315MOVEU.W Move Unsigned Word from MOVEU.WMemory to a Register (AGU)DescriptionThese operations move an unsig

Address Generation UnitSC140 DSP Core Reference Manual 2-312.3 Address Generation UnitThe AGU is one of the execution units in the SC140 core. The A

A-316 SC140 DSP Core Reference ManualMOVEU.WStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExamplemoveu.w (r

MOVEU.WSC140 DSP Core Reference Manual A-317Instruction Formats and OpcodesInstruction FieldsC4 DDDDD General RegistersDR HHHH Data/Address RegisterIn

A-318 SC140 DSP Core Reference ManualMOVEU.WEA MMM Effective Address NotationRn RRR Address Register000 (Rn+N0) 010 (Rn) 100 (Rn)+N0 110 (Rn)+N2001 (R

MPYSC140 DSP Core Reference Manual A-319MPY Signed Fractional Multiply (DALU) MPYDescriptionStatus and Conditions that Affect InstructionStatus and Co

A-320 SC140 DSP Core Reference ManualMPY0.010 $2000 1/4x 1.100$C000 –1/21.111 $F000 –1/8Example 2mpy d6,d6,d7Instruction Formats and OpcodesNote: ** i

MPYSC140 DSP Core Reference Manual A-321Dn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 101 D5 111 D7Note: Th

A-322 SC140 DSP Core Reference ManualMPYRMPYR Signed Fractional Multiply MPYRand Round (DALU)DescriptionStatus and Conditions that Affect InstructionS

MPYRSC140 DSP Core Reference Manual A-3230.100 0000 0000 0001$4001 x 0.100 0000 0000 0010$4002 0.010 0000 0000 0001 1000 0000 0000 0000$2001 8000round

A-324 SC140 DSP Core Reference ManualMPYR

MPYSUSC140 DSP Core Reference Manual A-325MPYSU Fractional Multiply MPYSUSigned By Unsigned (DALU) DescriptionStatus and Conditions that Affect Instru

2-32 SC140 DSP Core Reference ManualAddress Generation UnitAll sixteen address registers (R0–R15) as well as the NSP or ESP are used for generating ad

A-326 SC140 DSP Core Reference ManualMPYSUDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 101 D5 111 D7Note:

MPYUSSC140 DSP Core Reference Manual A-327MPYUS Fractional Multiply MPYUSUnsigned By Signed (DALU)DescriptionStatus and Conditions that Affect Instruc

A-328 SC140 DSP Core Reference ManualMPYUSInstruction FieldsDc,Dd ee Data Register PairsDn FFF Single Source/Destination Data Register00 D0,D1 01 D2

MPYUUSC140 DSP Core Reference Manual A-329MPYUU Fractional Multiply MPYUUUnsigned By Unsigned (DALU)DescriptionStatus and Conditions that Affect Instr

A-330 SC140 DSP Core Reference ManualMPYUUInstruction FieldsDc,Dd ee Data Register PairsDn FFF Single Source/Destination Data Register00 D0,D1 01 D2

NEGSC140 DSP Core Reference Manual A-331N-RNEG Negate (DALU) NEGDescription Status and Conditions that Affect InstructionStatus and Conditions Changed

A-332 SC140 DSP Core Reference ManualNEGInstruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDn FFF Single S

NOPSC140 DSP Core Reference Manual A-333NOP No Operation (PREFIX) NOPDescriptionStatus and conditions that Affect InstructionNone.Status and Condition

A-334 SC140 DSP Core Reference ManualNOTNOT Bitwise Complement (DALU) NOTDescriptionStatus and Conditions that Affect InstructionNone.Status and Condi

NOTSC140 DSP Core Reference Manual A-335Da JJJ Single Source Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 101 D5 111 D7Note: This instructi

Address Generation UnitSC140 DSP Core Reference Manual 2-33During every instruction cycle, the two AAUs can generate one 32-bit program memory address

A-336 SC140 DSP Core Reference ManualNOTNOT Binary Inversion of a 16-Bit Operand (BMU) NOTDescriptionStatus and Conditions that Affect InstructionNone

NOTSC140 DSP Core Reference Manual A-337Instruction Formats and OpcodesInstruction FieldsDR HHHH Data/Address RegisterInstruction Words Cycles Type Op

A-338 SC140 DSP Core Reference ManualNOT.WNOT.W Binary Inversion of a 16-Bit Operand NOT.W in Memory (BMU)DescriptionThese operations read from memory

NOT.WSC140 DSP Core Reference Manual A-339Examplenot.w (r1)Instruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterRegister/Memory Add

A-340 SC140 DSP Core Reference ManualOROR Bitwise Inclusive OR (DALU) ORDescriptionStatus and Conditions that Affect InstructionNone.Status and Condit

ORSC140 DSP Core Reference Manual A-341Dn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 101 D5 111 D7Note: Thi

A-342 SC140 DSP Core Reference ManualOROR Bitwise OR on a 16-Bit Operand (BMU) ORDescriptionStatus and Conditions that Affect InstructionNone.Status a

ORSC140 DSP Core Reference Manual A-343Instruction Formats and OpcodesInstruction FieldsDR HHHH Data/Address RegisterInstruction Words Cycles Type Opc

A-344 SC140 DSP Core Reference ManualOR.WOR.WBitwise OR on a 16-Bit Operand in Memory (BMU) OR.WDescriptionThese operations read from memory, modify t

OR.WSC140 DSP Core Reference Manual A-345Exampleor.w #$f01a,(r1) 1111 0000 0001 1010or 0001 0010 0011 0101 1111 0010 0011 1111Instruction Formats and

2-34 SC140 DSP Core Reference ManualAddress Generation Unit2.3.2 AGU Programming ModelThe programming model of the AGU is shown in Figure 2-13. The a

A-346 SC140 DSP Core Reference ManualOR.Ws16 AAAAAAAAAAAAAAAA Signed 16-bit SP address offset

POPSC140 DSP Core Reference Manual A-347POP Pop a Register from the Software Stack (AGU) POPDescriptionThese operations read the memory address pointe

A-348 SC140 DSP Core Reference ManualPOPStatus and Conditions that Affect InstructionStatus and Conditions Changed By InstructionExamplepop d3Instruct

POPSC140 DSP Core Reference Manual A-349De EEEEE Extension Pairs, Even Registers, and Loop Start RegistersDo eeeee Modifier Control, Odd Registers, an

A-350 SC140 DSP Core Reference ManualPOPNPOPN Pop a Register from the Software Stack POPNUsing the Normal Stack Pointer (AGU)DescriptionThese operatio

POPNSC140 DSP Core Reference Manual A-351Status and Conditions that Affect InstructionStatus and Conditions Changed By InstructionExamplepopn d6.e:d7.

A-352 SC140 DSP Core Reference ManualPOPNDe EEEEE Extension Pairs, Even Registers, and Loop Start RegistersDo eeeee Modifier Control, Odd Registers, a

PUSHSC140 DSP Core Reference Manual A-353PUSH Push a Register onto the Software Stack (AGU) PUSHDescriptionThese operations move an even or odd regis

A-354 SC140 DSP Core Reference ManualPUSHStatus and Conditions that Affect InstructionStatus and Conditions Changed By InstructionNoneExamplepush d0.e

PUSHSC140 DSP Core Reference Manual A-355Instruction FieldsDe EEEEE Extension Pairs, Even Registers, and Loop Start RegistersDo eeeee Modifier Control

Address Generation UnitSC140 DSP Core Reference Manual 2-352.3.2.1 Address Registers (R0–R15)The sixteen 32-bit address registers R0–R15 can contain

A-356 SC140 DSP Core Reference ManualPUSHNPUSHN Push a Register onto the Software Stack PUSHNUsing the Normal Stack Pointer (AGU)DescriptionThese oper

PUSHNSC140 DSP Core Reference Manual A-357Status and Conditions that Affect InstructionStatus and Conditions Changed By InstructionExamplepushn d0.e:d

A-358 SC140 DSP Core Reference ManualPUSHNInstruction Formats and OpcodesInstruction FieldsDe EEEEE Extension Pairs, Even Registers, and Loop Start Re

RNDSC140 DSP Core Reference Manual A-359RND Round (DALU) RNDDescriptionTwo types of rounding can be used: convergent rounding (round to the nearest ev

A-360 SC140 DSP Core Reference ManualRNDStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionExample 1rnd d1,d5Exa

RNDSC140 DSP Core Reference Manual A-361Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDn FFF Single S

A-362 SC140 DSP Core Reference ManualROLROL Rotate One Bit Left Through the Carry Bit (DALU) ROLDescriptionStatus and Conditions that Affect Instructi

ROLSC140 DSP Core Reference Manual A-363Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDn FFF Single S

A-364 SC140 DSP Core Reference ManualRORROR Rotate One Bit Right Through the Carry Bit (DALU) RORDescriptionStatus and Conditions that Affect Instruc

RORSC140 DSP Core Reference Manual A-365Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDn FFF Single S

2-36 SC140 DSP Core Reference ManualAddress Generation Unit2.3.2.2.1 Shadow Stack Pointer RegistersBoth stack pointers have shadow registers which c

A-366 SC140 DSP Core Reference ManualRORRTE Return From Exception (AGU) RTEDescriptionNote: Because RTE does not use RAS, returning from a subroutine

RORSC140 DSP Core Reference Manual A-367ExamplerteInstruction Formats and OpcodesRegister/Memory Address Before AfterESP$00000010 $00000008($000C)$00E

A-368 SC140 DSP Core Reference ManualRTEDRTED Return From Exception With a Delay Slot (AGU) RTEDDescriptionStatus and Conditions that Affect Instructi

RTEDSC140 DSP Core Reference Manual A-369ExamplertedInstruction Formats and OpcodesInstruction Commentmove.w #$2000,vba Load the vector base address r

A-370 SC140 DSP Core Reference ManualRTSRTS Return From Subroutine (AGU) RTSDescriptionNote: Because RTS uses the RAS mechanism, returning from an exc

RTSSC140 DSP Core Reference Manual A-371Instruction Formats and OpcodesInstruction WordsCycles1Note 1: RTS uses 3 cycles if the RAS is valid. RTS use

A-372 SC140 DSP Core Reference ManualRTSDRTSD Return From Subroutine With Delay Slot (AGU) RTSDDescriptionStatus and Conditions that Affect Instructio

RTSDSC140 DSP Core Reference Manual A-373Instruction Formats and OpcodesInstruction WordsCycles1Note 1: RTSD uses 3 cycles if the RAS is valid. RTSD u

A-374 SC140 DSP Core Reference ManualRTSTKRTSTK Restore PC from Stack (AGU) RTSTKDescriptionStatus and Conditions that Affect InstructionStatus and C

RTSTKSC140 DSP Core Reference Manual A-375ExamplertstkInstruction Formats and OpcodesInstruction Comment- - -jsr SUBJump to subroutine at SUB. Push th

Address Generation UnitSC140 DSP Core Reference Manual 2-372.3.2.6 Modifier Control Register (MCTL)The MCTL register is a 32-bit read/write register

A-376 SC140 DSP Core Reference ManualRTSTKDRTSTKD Restore PC from Stack RTSTKDUsing a Delay Slot (AGU)DescriptionStatus and Conditions that Affect In

RTSTKDSC140 DSP Core Reference Manual A-377ExamplertstkdInstruction Formats and OpcodesInstruction Comment- - -jsr SUBJump to subroutine at SUB. Push

A-378 SC140 DSP Core Reference ManualSAT.FSSAT.F Saturate Fractional Data Register SAT.F(DALU)DescriptionStatus and Conditions that Affect Instructio

SAT.FSC140 DSP Core Reference Manual A-379Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDa JJJ Single

A-380 SC140 DSP Core Reference ManualSAT.LSAT.L Saturate 32-Bit Data Register SAT.L (DALU)DescriptionStatus and Conditions that Affect InstructionNone

SAT.LSC140 DSP Core Reference Manual A-381Instruction FieldsDn FFF Single Source/Destination Data Register000 D0 010 D2 100 D4 110 D6001 D1 011 D3 1

A-382 SC140 DSP Core Reference ManualSBCSBC Subtract With Borrow (DALU) SBCDescriptionStatus and Conditions that Affect InstructionStatus and Conditio

SBCSC140 DSP Core Reference Manual A-383The two instructions shown can be used for a 64-bit subtraction, with the sub d0,d1,d1 performing the lower 32

A-384 SC140 DSP Core Reference ManualSBRSBR Subtract And Round (DALU) SBRDescriptionStatus and Conditions that Affect InstructionStatus and Conditions

SBRSC140 DSP Core Reference Manual A-3850010 1010 1110 0111 0000 0000 1000$2AE7 0080– 0001 0101 0011 0000 0000 0000 0011$1539 00300001 0101 1010 1110

SC140 DSP Core Reference Manual viiChapter 5Program Control5.1 Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-38 SC140 DSP Core Reference ManualAddress Generation Unit2.3.3 Addressing ModesThe SC140 core provides four types of addressing modes: • Register d

A-386 SC140 DSP Core Reference ManualSKIPLSSKIPLS Skip Loop If LC Less Than or SKIPLSEqual to Zero (AGU)DescriptionStatus and Conditions that Affect

SKIPLSSC140 DSP Core Reference Manual A-387Instruction Formats and OpcodesInstruction FieldsInstruction Words Cycles Type Opcode15 8 7 0SKIPLS label 2

A-388 SC140 DSP Core Reference ManualSTOPSTOP Stop Instruction Processing (AGU) STOPDescriptionStatus and Conditions that Affect InstructionStatus and

SUBSC140 DSP Core Reference Manual A-389SUB Subtract (DALU) SUBDescriptionStatus and Conditions that Affect InstructionStatus and Conditions Changed b

A-390 SC140 DSP Core Reference ManualSUBExample 2sub d0,d1,d2Scaling up is set in SR[5], so L2 bit is set from overflow from bit 30.Instruction Format

SUBSC140 DSP Core Reference Manual A-391Instruction FieldsDa,Db JJJJJ Data Register PairsDa,Da jj Data Register PairsDn FFF Single Source/Destinatio

A-392 SC140 DSP Core Reference ManualSUB2SUB2 Subtract Two 16-Bit Values (DALU) SUB2DescriptionStatus and Conditions that Affect InstructionNone.Statu

SUB2SC140 DSP Core Reference Manual A-393Instruction Formats and OpcodesInstruction FieldsDn FFF Single Source/Destination Data RegisterDa JJJ Sin

A-394 SC140 DSP Core Reference ManualSUBASUBA Subtract (AGU) SUBADescriptionThis instruction subtracts an immediate or an AGU register from another AG

SUBASC140 DSP Core Reference Manual A-395Instruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination Re

Address Generation UnitSC140 DSP Core Reference Manual 2-39• Post-decrement, (Rn)- —The operand address is in the address register. After the operand

A-396 SC140 DSP Core Reference ManualSUBLSUBL Shift Left and Subtract (DALU) SUBLDescriptionStatus and Conditions that Affect InstructionStatus and Co

SUBLSC140 DSP Core Reference Manual A-397Example 2subl d0,d1Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction Fie

A-398 SC140 DSP Core Reference ManualSUBNC.WSUBNC.W Subtract Without Changing SUBNC.Wthe Carry Bit (DALU)DescriptionStatus and Conditions that Affect

SUBNC.WSC140 DSP Core Reference Manual A-399Instruction Formats and OpcodesInstruction FieldsDn FFF Single Source/Destination Data RegisterInstructi

A-400 SC140 DSP Core Reference ManualSXT.xSXT.x Sign-Extension (DALU) SXT.xDescriptionThese operations sign-extend a data register. The sign bit (bit

SXT.xSC140 DSP Core Reference Manual A-401Example 3sxt.l d3Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction Fiel

A-402 SC140 DSP Core Reference ManualSXTA.xSXTA.x Sign-Extension (AGU) SXTA.xDescriptionThese operations sign-extend an AGU register (address or offse

SXTA.xSC140 DSP Core Reference Manual A-403Instruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination

A-404 SC140 DSP Core Reference ManualTFRT-ZTFR Transfer Data Register to Data Register (DALU) TFRDescriptionStatus and Conditions that Affect Instruct

TFRSC140 DSP Core Reference Manual A-405Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction FieldsDa JJJ Single S

2-40 SC140 DSP Core Reference ManualAddress Generation Unitactive SP register are unchanged. The type of arithmetic used is always linear. An example

A-406 SC140 DSP Core Reference ManualTFRATFRA Transfer Address Register (AGU) TFRADescriptionStatus and Conditions that Affect InstructionStatus and

TFRASC140 DSP Core Reference Manual A-407Rx RRRR AGU Source/Destination Register0000 N0 0100 — 1000 R0 1100 R40001 N1 0101 — 1001 R1 1101 R50010 N2 01

A-408 SC140 DSP Core Reference ManualTFRATFRA Move the Other Stack Pointer TFRA to/from a Register (AGU)DescriptionStatus and Conditions that Affect

TFRASC140 DSP Core Reference Manual A-409Exampletfra r0,ospInstruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterRegister/Memory Add

A-410 SC140 DSP Core Reference ManualTFRcTFRc Conditionally Transfer Data Register TFRc to Data Register (DALU)DescriptionStatus and Conditions that A

TFRcSC140 DSP Core Reference Manual A-411Instruction Formats and OpcodesInstruction FieldsDa JJJ Single Source Data RegisterDn FFF Single Source/D

A-412 SC140 DSP Core Reference ManualTRAPTRAP Execute a Software Exception (AGU) TRAPDescriptionTRAP The starting address of the exception processing

TRAPSC140 DSP Core Reference Manual A-413Status and Conditions Changed by InstructionExample 1trapInstruction Formats and OpcodesRegister Address Bit

A-414 SC140 DSP Core Reference ManualTSTEQTSTEQ Test for Equal to Zero (DALU) TSTEQDescriptionStatus and Conditions that Affect InstructionNone.Status

TSTEQA.xSC140 DSP Core Reference Manual A-415TSTEQA.x Test for Equal to Zero (AGU) TSTEQA.xDescriptionSet the T bit if the source AGU register (Rx) is

Address Generation UnitSC140 DSP Core Reference Manual 2-412.3.3.4 Special Addressing Modes The special addressing modes do not use an address regis

A-416 SC140 DSP Core Reference ManualTSTEQA.xInstruction Formats and OpcodesInstruction FieldsRx RRRR AGU Source/Destination RegisterInstruction Words

TSTGESC140 DSP Core Reference Manual A-417TSTGE Test for Greater Than TSTGEor Equal to Zero (DALU)DescriptionStatus and Conditions that Affect Instruc

A-418 SC140 DSP Core Reference ManualTSTGEA.LTSTGEA.L Test for Greater Than or Equal TSTGEA.Lto Zero (AGU)DescriptionStatus and Conditions that Affect

TSTGEA.LSC140 DSP Core Reference Manual A-419Instruction Formats and OpcodesInstruction FieldsRx RRRR AGU Source/Destination RegisterInstruction Words

A-420 SC140 DSP Core Reference ManualTSTGTTSTGT Test for Greater Than Zero (DALU) TSTGTDescriptionStatus and Conditions that Affect InstructionNone.St

TSTGTASC140 DSP Core Reference Manual A-421TSTGTA Test for Greater Than Zero (AGU) TSTGTADescriptionStatus and Conditions that Affect InstructionStatu

A-422 SC140 DSP Core Reference ManualVSLVSL Viterbi Shift Left Move (AGU) VSLNote: In the operation fields, the term << 1 indicates shift left

VSLSC140 DSP Core Reference Manual A-423DescriptionThe VSL instructions are intended to optimize the implementation of the Viterbi decoder algorithm.

A-424 SC140 DSP Core Reference ManualVSLStatus and Conditions that Affect InstructionStatus and Conditions Changed by InstructionNone.Examplevsl.2w d1

VSLSC140 DSP Core Reference Manual A-425Instruction Formats and OpcodesInstruction FieldsRn RRR Address RegisterInstruction Words Cycles Type Opcode15

2-42 SC140 DSP Core Reference ManualAddress Generation Unit2.3.3.5 Memory Access WidthThe SC140 core supports variable width access to data memory.

A-426 SC140 DSP Core Reference ManualWAITWAIT Wait for an Interrupt (AGU) WAITDescriptionOperation Assembler SyntaxEnters the low-power standby WAIT p

WAITSC140 DSP Core Reference Manual A-427Status and Conditions that Affect InstructionStatus and Conditions Changed by InstructionNoneInstruction Form

A-428 SC140 DSP Core Reference ManualZXT.xZXT.x Zero Extension (DALU) ZXT.xDescriptionThese operations zero-extend a data register.Status and Conditio

ZXT.xSC140 DSP Core Reference Manual A-429Example 3zxt.l d0Instruction Formats and OpcodesNote: ** indicates serial grouping encoding.Instruction Fiel

A-430 SC140 DSP Core Reference ManualZXTA.xZXTA.x Zero Extension (AGU) ZXTA.xDescriptionThese operations zero-extend an AGU source register (address o

ZXTA.xSC140 DSP Core Reference Manual A-431Instruction Formats and OpcodesInstruction Fieldsrx rrrr AGU Source RegisterRx RRRR AGU Source/Destination

A-432 SC140 DSP Core Reference ManualZXTA.x

SC140 DSP Core Reference Manual B-1Appendix BStarCore RegistryThe StarCore registry (SCR) is a system that identifies the core version. B.1 Using th

B-2 SC140 DSP Core Reference ManualStarCore RegistryIn SC100 implementations, the SCID is defined at the SoC level by strapping a set of core interfac

Index I-1AAAU (address arithmetic unit) 1-3, 2-4ABS A-20Accelerator 2-5, 6-57Access width support 2-42ADC A-22ADD A-24ADD2 A-27ADDA A-29ADDL1A A-32ADD

Address Generation UnitSC140 DSP Core Reference Manual 2-43Table 2-19 summarizes the memory address alignment rule for each type of memory access.Tabl

I-2 IndexCCS (comparator condition selection bits) 4-60Change-of-flow instructions 2-68CLB A-113CLR A-115CMPEQ A-117CMPEQ.W A-119CMPEQA A-121CMPGT A-1

Index I-3 CS 4-55EDCAEN 4-55EDCAST5-0 (EDCA #5-0 status) 4-42EDCD (data event detection channel) 4-24, 4-58control register (EDCD_CTRL) 4-58mask regis

I-4 IndexESEL_DTB (ES mask disable trace register) 4-26, 4-65ESEL_ETB (ES mask enable trace register) 4-26, 4-64ESP (exception stack pointer register)

Index I-5 BMSET.W A-82BMTSET A-84BMTSET.W A-86BMTSTC A-89BMTSTC.W A-91BMTSTS A-94BMTSTS.W A-96BRA A-99BRAD A-101BREAK A-103BSR A-105BSRD A-107BT A-109

I-6 IndexNOT.W A-338OR A-340, A-342OR.W A-344POP A-347POPN A-350PUSH A-353PUSHN A-356RND A-359ROL A-362ROR A-364RTE A-366RTED A-368RTS A-370RTSD A-372

Index I-7 MIN A-253Modifier registers (M0-M3) 2-36Modulo adder 2-33Modulo addressing 2-4Modulo addressing mode 2-45Move instructions 2-51, 2-52fractio

I-8 IndexRM (rounding mode bit) 3-5RND A-359ROL A-362ROR A-364Rounding 2-21, 2-23RTE A-366RTED A-368RTS A-370RTSD A-372RTSTK A-374RTSTKD A-376SS (scal

Index I-9 Trace unitcontrol register (TB_CTRL) 4-65read pointer register (TB_RD) 4-69register set 4-30virtual register (TB_BUFF) 4-69write pointer reg

I-10 Index

SC140 DSP Core Reference Manual i

2-44 SC140 DSP Core Reference ManualAddress Generation UnitNote: The “—” that appears in the “R0-R7 Uses MCTL” heading means that it is not applicable

Address Generation UnitSC140 DSP Core Reference Manual 2-452.3.4 Address Modifier ModesThe AAU supports linear, reverse-carry, modulo, and multiple w

2-46 SC140 DSP Core Reference ManualAddress Generation Unitregister Rn has one Mj register assigned to it by encoding in the MCTL. The lower boundary

Address Generation UnitSC140 DSP Core Reference Manual 2-47Table 2-21 describes the modulo register values and the corresponding address calculation.2

viii SC140 DSP Core Reference Manual5.5.5 Fast Return from Subroutines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-365.6

2-48 SC140 DSP Core Reference ManualAddress Generation UnitTable 2-22 describes the modulo register Mj values and the corresponding multiple wrap-arou

Address Generation UnitSC140 DSP Core Reference Manual 2-492.3.6 Bit Mask InstructionsThe SC140 core provides bit mask instructions on all address re

2-50 SC140 DSP Core Reference ManualAddress Generation UnitTable 2-24 lists the arithmetic instructions that are executed in the BMU.2.3.6.1 Bit Mas

Address Generation UnitSC140 DSP Core Reference Manual 2-512.3.6.1.1 Example of Normal Usage of the Semaphoring MechanismThe following sequence acce

2-52 SC140 DSP Core Reference ManualAddress Generation UnitThe suffix just after the period in the MOVE nomenclature indicates the following:• B = Byt

Address Generation UnitSC140 DSP Core Reference Manual 2-53Integer moves from memory (byte, word, long, two long) are right-aligned in the destination

2-54 SC140 DSP Core Reference ManualAddress Generation Unit.Figure 2-17. Fractional Move InstructionsThe four instructions MOVES.F, MOVES.2F, MOVES.

Memory InterfaceSC140 DSP Core Reference Manual 2-55The extension bits of the even data register occupy bits 0 to 8 (bit 8 is the limit bit). The exte

2-56 SC140 DSP Core Reference ManualMemory Interface• Memory must resolve access ordering on a cycle by cycle basis. All accesses on a given cycle mus

Memory InterfaceSC140 DSP Core Reference Manual 2-57The two data buses that connect between the core and the memory are each 64 bits wide. Instruction

SC140 DSP Core Reference Manual ix6.7 Core Assembly Syntax with an ISAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-636.7.1 Id

2-58 SC140 DSP Core Reference ManualMemory InterfaceTable 2-26 describes the data representation for each 64-bit row in Figure 2-21.2.4.1.3 Data Mov

Memory InterfaceSC140 DSP Core Reference Manual 2-59Figure 2-22. Data Transfer in Big and Little Endian ModesFor single-register moves, assuming an

2-60 SC140 DSP Core Reference ManualMemory Interface2.4.1.4 Multi-Register MovesFor accesses involving more than one register, such as with MOVE.2W

Memory InterfaceSC140 DSP Core Reference Manual 2-61This is the desired result. This effect is achieved in little endian mode through logic in the cor

2-62 SC140 DSP Core Reference ManualMemory Interface2.4.1.5 Instruction Word TransfersInstruction words are transferred to the core from memory over

Memory InterfaceSC140 DSP Core Reference Manual 2-63Figure 2-25 shows the memory accesses to the same memory area by both program fetches as well as d

2-64 SC140 DSP Core Reference ManualMemory Interface2.4.1.6 Memory Access Behavior in Big/Little Endian ModesTable 2-27 shows the representation of

Memory InterfaceSC140 DSP Core Reference Manual 2-65MOVE.L(Extension)A0 = L1A1 = B1A2 = L0A3 = A1A0 = A1A1 = L0A2 = B1A3 = L1MOVE.2L A0 = AA1 = BA2 =

2-66 SC140 DSP Core Reference ManualMemory InterfaceNotes:1. Data selected according to VF0 bit in SR, selects D3.l<<1 if VF0=1, D1.L<<1 i

Memory InterfaceSC140 DSP Core Reference Manual 2-67Table 2-28 shows the representation of the stack support instructions in big and little endian mod